Method to etch non-volatile metal materials
US-2015340603-A1 · Nov 26, 2015 · US
Variable resistance memory device and methods of forming the same
US9318704B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9318704-B2 |
| Application number | US-201514717575-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 20, 2015 |
| Priority date | Sep 14, 2012 |
| Publication date | Apr 19, 2016 |
| Grant date | Apr 19, 2016 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Variable resistance memory devices and methods of forming the same are disclosed. The devices may include an additional barrier layer that is a portion of a variable resistance layer and that is formed before forming a horizontal electrode layer. Due to the presence of the additional barrier layer, it may be possible to cure loss or damage of the variable resistance layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of fabricating a variable resistance memory device, comprising: alternatingly stacking a plurality of sacrificial layers and a plurality of insulating layers on a layer; patterning the insulating layers and the sacrificial layers to form a vertical electrode hole; forming a first barrier layer on a sidewall of the vertical electrode hole; forming a switching layer on a sidewall of the first barrier layer; forming a vertical electrode in the vertical electrode hole, the vertical electrode being connected to the layer; patterning the insulating layers and the sacrificial layers to form a groove spaced apart from the vertical electrode hole; removing the sacrificial layers through the groove to form an empty space; conformally forming a second barrier layer in the empty space; and filling the empty space with a horizontal electrode layer. 2. The method of claim 1 , wherein the first barrier layer is partially removed during the removing of the sacrificial layers through the groove. 3. The method of claim 1 , wherein the forming of the second barrier layer and the horizontal electrode layer is performed in an in-situ manner.
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9318704B2 cover?
- Variable resistance memory devices and methods of forming the same are disclosed. The devices may include an additional barrier layer that is a portion of a variable resistance layer and that is formed before forming a horizontal electrode layer. Due to the presence of the additional barrier layer, it may be possible to cure loss or damage of the variable resistance layer.
- Who is the assignee on this patent?
- Seong Dongjun, Shin Yoocheol, Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H01L45/1675. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).