Array substrate and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9318612-B2
Application number	US-201414538243-A
Country	US
Kind code	B2
Filing date	Nov 11, 2014
Priority date	Nov 25, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

An array substrate includes: a substrate; a thin film transistor including a gate electrode, an oxide semiconductor layer and source and drain electrodes, wherein a first insulating layer of an inorganic insulating material is disposed between the gate electrode and the oxide semiconductor layer, and wherein a second insulating layer of an inorganic insulating material is disposed between the oxide semiconductor layer and the source and drain electrodes; a passivation layer on the thin film transistor; a first electrode on the passivation layer in the pixel region; and a first hydrogen absorbing layer on at least one of top and bottom surfaces of the first insulating layer, top and bottom surfaces of the second insulating layer and top and bottom surfaces of the passivation layer, the first hydrogen absorbing layer including plurality of particles spaced apart from each other and including one of nickel, palladium and platinum.

First claim

What is claimed is:

1. An array substrate comprising:
a substrate including a pixel region;
a thin film transistor in the pixel region, the thin film transistor including a gate electrode, an oxide semiconductor layer and source and drain electrodes spaced apart from each other, wherein a first insulating layer of an inorganic insulating material is disposed between the gate electrode and the oxide semiconductor layer, and wherein a second insulating layer of an inorganic insulating material is disposed between the oxide semiconductor layer and the source and drain electrodes;
a passivation layer on the thin film transistor, the passivation layer having a drain contact hole exposing the drain electrode;
a first electrode on the passivation layer in the pixel region, the first electrode connected to the drain electrode through the drain contact hole; and
a first hydrogen absorbing layer on at least one of top and bottom surfaces of the first insulating layer, at least one of top and bottom surfaces of the second insulating layer, or at least one of top and bottom surfaces of the passivation layer, the first hydrogen absorbing layer including a plurality of particles spatially and electrically separated from each other, the plurality of particles including one of nickel, palladium and platinum,
wherein the oxide semiconductor layer directly and physically contacts the first hydrogen absorbing layer.

2. The array substrate of claim 1 , wherein the first hydrogen absorbing layer is configured to absorb a hydrogen diffused from the first insulating layer, the second insulating layer and the passivation layer to constitute an interstitial compound storing the hydrogen.

3. The array substrate of claim 2 , wherein the interstitial compound has an insulation property.

4. The array substrate of claim 1 , wherein the first insulating layer is a gate insulating layer between the gate electrode and the oxide semiconductor layer and the second insulating layer is an etch stopper between the oxide semiconductor layer and the source and drain electrodes.

5. The array substrate of claim 4 , wherein the etch stopper has one of an island shape covering a central portion of the oxide semiconductor layer and a plate shape covering an entire surface of the substrate having the oxide semiconductor layer with semiconductor contact holes exposing end portions of the oxide semiconductor layer.

6. The array substrate of claim 1 , wherein the first insulating layer is a gate insulating layer between the oxide semiconductor layer and the gate electrode and the second insulating layer is an interlayer insulating layer between the gate electrode and the source and drain electrodes.

7. The array substrate of claim 6 , further comprising a buffer layer of an inorganic insulating material between the substrate and the oxide semiconductor layer.

8. The array substrate of claim 7 , further comprising a second hydrogen absorbing layer on one of top and bottom surfaces of the buffer layer, wherein the second hydrogen absorbing layer includes a plurality of particles spatially and electrically separated from each other and the plurality of particles include one of nickel, palladium and platinum.

9. The array substrate of claim 1 , further comprising:
a bank layer on the first electrode, the bank layer covering a boundary portion of the first electrode contacting the drain electrode;
an emitting material layer on the first electrode; and
a second electrode on the emitting material layer.

10. The array substrate of claim 9 , further comprising a planarization layer on the passivation layer, wherein the planarization layer and the passivation layer have the drain contact hole and the first electrode is disposed on the planarization layer.

11. The array substrate of claim 10 , further comprising a color filter layer between the passivation layer and the planarization layer.

12. A method of fabricating an array substrate, comprising:
forming a thin film transistor in a pixel region on a substrate, the thin film transistor including a gate electrode, an oxide semiconductor layer and source and drain electrodes spaced apart from each other, wherein a first insulating layer of an inorganic insulating material is disposed between the gate electrode and the oxide semiconductor layer, and wherein a second insulating layer of an inorganic insulating material is disposed between the oxide semiconductor layer and the source and drain electrodes;
forming a passivation layer on the thin film transistor, the passivation layer having a drain contact hole exposing the drain electrode;
forming a first electrode on the passivation layer in the pixel region, the first electrode connected to the drain electrode through the drain contact hole; and
forming a first hydrogen absorbing layer on at least one of top and bottom surfaces of the first insulating layer, at least one of top and bottom surfaces of the second insulating layer, or at least one of top and bottom surfaces of the passivation layer, the first hydrogen absorbing layer including a plurality of particles spatially and electrically separated from each other, the plurality of particles including one of nickel, palladium and platinum,
wherein the oxide semiconductor layer of the thin film transistor is formed directly and physically contacting the first hydrogen absorbing layer.

13. The method of claim 12 , wherein forming the first hydrogen absorbing layer includes depositing a metallic material including one of nickel, palladium and platinum such that the first hydrogen absorbing layer has a thickness of about 0.1 Å to about 9 Å.

14. The method of claim 12 , wherein the first insulating layer is a gate insulating layer between the gate electrode and the oxide semiconductor layer and the second insulating layer is an etch stopper between the oxide semiconductor layer and the source and drain electrodes.

15. The method of claim 12 , wherein the first insulating layer is a gate insulating layer between the oxide semiconductor layer and the gate electrode and the second insulating layer is an interlayer insulating layer between the gate electrode and the source and drain electrodes.

16. The method of claim 15 , further comprising forming a buffer layer of an inorganic insulating material between the substrate and the oxide semiconductor layer.

17. The method of claim 16 , further comprising forming a second hydrogen absorbing layer on one of top and bottom surfaces of the buffer layer, wherein the second hydrogen absorbing layer includes a plurality of particles spatially and electrically separated from each other and the plurality of particles include one of nickel, palladium and platinum.

18. The method of claim 12 , further comprising:
forming a bank layer on the first electrode, the bank layer covering a boundary portion of the first electrode contacting the drain electrode;
forming an emitting material layer on the first electrode; and
forming a second electrode on the emitting material layer.

19. The method of claim 18 , further comprising forming a planarization layer on the passivation layer, wherein the planarization layer and the passivation layer have the drain contact hole and the first electrode is disposed on the planarization layer.

20. The method of claim 19 , further comprising forming a color filter layer between the passivation layer and the planarization layer.

Assignees

• Lg Display Co Ltd

Inventors

• Seo Hyun-Sik
• Seo Kyung-Han

Classifications

• H10K59/874

  including getter material or desiccant · CPC title

• H10K59/873

  Encapsulations · CPC title

• H10K50/10

  OLEDs or polymer light-emitting diodes [PLED] · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title