Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9318601-B2
Application number	US-201414300990-A
Country	US
Kind code	B2
Filing date	Jun 10, 2014
Priority date	Jun 10, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate, having a first conductivity type;
a semiconductor layer formed over the semiconductor substrate, having the first conductivity type;
a gate structure disposed over a portion of the semiconductor layer;
a first doped region disposed in a portion of the semiconductor layer adjacent to a first side of the gate structure, having the first conductivity type;
a second doped region disposed in a portion of the semiconductor layer adjacent to a second side of the gate structure opposite to the first side, having a second conductivity type opposite to the first conductivity type;
a third doped region disposed in a portion of the first doped region, having the second conductivity type;
a fourth doped region disposed in a portion of the second doped region, having the second conductivity type;
a plurality of fifth doped regions, separately disposed in a plurality portions of the second doped region, having the first conductivity type, wherein the fifth doped regions are formed between the fourth doped region and the gate structure and the fifth doped regions physically contact the fourth doped region;
a sixth doped region disposed in a portion of the semiconductor layer under the first doped region, contacting the semiconductor substrate; and
a conductive contact formed in a portion of the third doped region and the first doped region, contacting the sixth doped region,
wherein the conductive contact does not extend into the sixth doped region.

2. The semiconductor device as claimed in claim 1 , wherein the first conductivity type is P type and the second conductivity type is N type.

3. The semiconductor device as claimed in claim 1 , wherein the third doped region is a source region, and the fourth doped region is a drain region.

4. The semiconductor device as claimed in claim 1 , wherein the fifth doped regions and the second doped region adjacent thereto form a super-junction structure.

5. The semiconductor device as claimed in claim 1 , wherein the fifth doped regions are formed with a rectangular configuration from a top view.

6. The semiconductor device as claimed in claim 1 , wherein the fifth doped regions are formed with a hollow-rectangular configuration from a top view.

7. The semiconductor device as claimed in claim 6 , further comprising an insulating layer formed in a plurality of portions of the semiconductor layer, wherein the insulating layer is surrounded by each of the fifth doped regions, respectively.

8. The semiconductor device as claimed in claim 1 , wherein the conductive contact comprises a first conductive layer, and a second conductive layer is surrounded by the first conductive layer.

9. A method for fabricating a semiconductor device, comprising:
providing a semiconductor substrate, having a first conductivity type;
forming a semiconductor layer over the semiconductor substrate, having the first conductivity type;
forming a gate structure over a portion of the semiconductor layer;
forming a first doped region in a portion of the semiconductor layer adjacent to a first side of the gate structure, having the first conductivity type;
forming a second doped region in a portion of the semiconductor layer adjacent to a second side of the gate structure opposite to the first side, having a second conductivity type opposite to the first conductivity type;
forming a third doped region in a portion of the first doped region, having the second conductivity type;
forming a fourth doped region in a portion of the second doped region, having the second conductivity type opposite to the first conductivity type;
forming a plurality of fifth doped regions in a plurality portions of the second doped region, having the first conductivity type, wherein the fifth doped regions are formed between the fourth doped region and the gate structure and the fifth doped regions physically contact the fourth doped region;
forming an insulating layer over the second doped region, the gate structure, and a portion of the third doped region;
forming a trench in a portion of the third doped region and the first doped region, exposing a portion of the semiconductor layer under the first doped region;
performing an ion implantation process, implanting dopants of the first conductive type in the semiconductor layer exposed by the trench, thereby forming a sixth doped region, wherein the sixth doping region physically contacts with the semiconductor substrate; and
forming a conductive contact in the trench, wherein the conductive contact physically contacts with the sixth doped region and does not extend into the sixth doped region.

10. The method as claimed in claim 9 , wherein the first conductivity type is P type and the second conductivity type is N type.

11. The method as claimed in claim 9 , wherein the third doped region is a source region and the fourth doped region is a drain region.

12. The method as claimed in claim 9 , wherein the fifth doped regions and the second doped region adjacent thereto form a super junction structure.

13. The method as claimed in claim 9 , wherein the fifth doped regions are formed with a rectangular configuration from a top view.

14. The method as claimed in claim 9 , wherein the fifth doped regions are formed with a hollow-rectangular configuration from a top view.

15. The method as claimed in claim 9 , further comprising forming an insulating layer in a plurality of portions of the semiconductor layer, wherein the insulating layer is surrounded by each of the fifth doped regions, respectively.

16. The method as claimed in claim 9 , wherein the conductive contact comprises a first conductive layer, and a second conductive layer is surrounded by the first conductive layer.

Assignees

• Vanguard Int Semiconduct Corp

Inventors

• Kumar Manoj
• Hung Pei-Heng
• Sulistyanto Priyono Tri
• Lee Chia-Hao
• Liao Chih-Cherng
• Tu Shang-Hui

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D64/111

  Field plates · CPC title

• H10D64/254

  for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts · CPC title