Transistor device and materials for making

Patent metadata

Field	Value
Publication number	US-9318591-B2
Application number	US-201214006158-A
Country	US
Kind code	B2
Filing date	Mar 22, 2012
Priority date	Mar 22, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

This application relates to graphene based heterostructures and transistor devices comprising graphene. The hetero-structures comprise i) a first graphene layer; ii) a spacer layer and iii) a third graphene. The transistors comprise (i) an electrode, the electrode comprising a graphene layer, and (ii) an insulating barrier layer.

First claim

The invention claimed is:

1. A graphene heterostructure having:
a first graphene layer, shaped to form a first structure comprising at least one contact region;
a second graphene layer, shaped to form a second structure comprising at least one contact region; and
a spacer positioned between the first graphene layer and the second graphene layer, wherein the spacer has a thickness in the range 3 to 8 layers of one or more materials;
wherein the graphene heterostructure includes two or more contacts, including a source contact and a drain contact; and
wherein the source contact is positioned on at least one of the contact regions of the first structure; and
wherein the drain contact is positioned on at least one of the contact regions of the second structure.

2. The graphene heterostructure according to claim 1 , wherein the spacer includes hexagonal boron-nitride.

3. The graphene heterostructure according to claim 1 , wherein the spacer lies directly next to the first graphene layer, and the second graphene layer lies directly next to the spacer.

4. The graphene heterostructure according to claim 1 , wherein the spacer has a thickness of 10 nm or less.

5. The graphene heterostructure according to claim 4 , wherein the spacer has a thickness in the range 2 nm to 4 nm.

6. The graphene heterostructure according to claim 1 , wherein the first graphene layer is a single sheet of graphene, and the second graphene layer is a single sheet of graphene.

7. The graphene heterostructure according to claim 1 , wherein the graphene heterostructure includes a base layer on which the first graphene layer is positioned.

8. The graphene heterostructure according to claim 7 , wherein the base layer includes hexagonal boron-nitride.

9. The graphene heterostructure according to claim 7 , wherein the graphene heterostructure includes a substrate on which the base layer is positioned.

10. A transistor comprising:
a source electrode;
a drain electrode; and
an insulating barrier in contact with and situated between both the source electrode and the drain electrode, the insulating barrier comprising from 3 to 8 layers of one or more materials;
wherein at least one of the source electrode and the drain electrode comprises a layer of graphene and the other electrode comprises a layer of a conductive material.

11. The graphene heterostructure according to claim 1 , wherein the graphene heterostructure is comprised in a transistor.

12. The transistor of claim 10 , wherein the transistor is a quantum tunnelling transistor.

13. A transistor comprising:
a source electrode;
a drain electrode; and
an insulating barrier in contact with and situated between both the source electrode and the drain electrode;
wherein the thickness of the insulating barrier layer is selected to provide a quantum tunnelling electron transport between the source electrode and the drain electrode; and
wherein at least one of the source electrode and the drain electrode comprises a layer of graphene and the other electrode comprises a layer of a conductive material.

14. A graphene heterostructure having:
a first graphene layer, shaped to form a first structure comprising at least one contact region;
a second graphene layer, shaped to form a second structure comprising at least one contact region; and
a spacer positioned between the first graphene layer and the second graphene layer, wherein the spacer has a thickness in the range 1 to 30 layers of one or more materials;
wherein the graphene heterostructure includes two or more contacts, including a source contact and a drain contact; and
wherein the source contact is positioned on at least one of the contact regions of the first structure; and
wherein the drain contact is positioned on at least one of the contact regions of the second structure.

Assignees

• Geim Andre
• Novoselov Konstantin
• Gorbachev Roman
• Ponomarenko Leonid
• Britnell Liam
• Univ Manchester

Inventors

• Geim Andre
• Novoselov Konstantin
• Gorbachev Roman
• Ponomarenko Leonid
• Britnell Liam

Classifications

• H10P14/00

  Formation of materials, e.g. in the shape of layers or pillars · CPC title

• H10D30/43 Primary

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/47

  having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] · CPC title

• H10D64/68

  characterised by the insulator, e.g. by the gate insulator · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title