High voltage semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9318586-B2
Application number	US-201313974558-A
Country	US
Kind code	B2
Filing date	Aug 23, 2013
Priority date	Sep 21, 2012
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

According to example embodiments of inventive concepts: a semiconductor device includes: first and second trench gates extending long in one direction in a substrate; third and fourth trench gates in the substrate, the third and fourth trench gates connecting the first and second trench gates with each other; a first region defined in the substrate by the first to fourth trench gates and surrounded by the first to fourth trench gates; and a second region and a third region defined in the substrate. The second region is in surface contact with the first region. The third region is in point contact with the first region. The first region includes a first high-voltage semiconductor device including a body of a first conduction type and an emitter of a second conduction type in the body. Floating wells of the first conduction type are in the second region and the third region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
first and second trench gates extending long in one direction in the substrate;
third and fourth trench gates in the substrate,
a fifth trench gate extending in the substrate parallel to the first and second trench gates;
a sixth trench gate extending in the substrate parallel to the third and fourth trench gates, the third, fourth and sixth trench gates connecting the first, second, and fifth trench gates to each other;
a first region defined in the substrate by the first to fourth trench gates,
the first region being surrounded by the first to fourth trench gates,
the first region including a first high-voltage semiconductor device,
the first high-voltage semiconductor device including a body and an emitter in the body,
the body being a first conduction type, and
the emitter being a second conduction type that is opposite the first conduction type; and

a second region and a third region defined in the substrate,
the second region being defined by the first, second, fourth, and sixth trench gates,
the third region being defined by the second, fourth, fifth, and sixth trench gates,
the second region being in surface contact with the first region,
the third region being in point contact with the first region,
the second region and the third region including floating wells that are the first conduction type.

2. The semiconductor device of claim 1 , wherein
a vertical thickness of the body is less than a vertical thickness of the first trench gate, and
a vertical thickness of the floating wells is more than the vertical thickness of the body.

3. The semiconductor device of claim 2 , wherein the vertical thickness of the floating wells is thicker than the vertical thickness of the first trench gate.

4. The semiconductor device of claim 1 , wherein a length of the second region in the one direction is longer than a length of the first region in the one direction.

5. The semiconductor device of claim 1 , further comprising:
a seventh trench gate in the substrate; and
a second high-voltage semiconductor device in the substrate between the fifth and seventh trench gates, wherein
the fifth and seventh trench gates extend long in the one direction, and
the first, second, fifth, and seventh trench gates are arranged in order.

6. The semiconductor device of claim 5 , wherein a length between the first trench gate and the second trench gate is shorter than a length between the second trench gate and the fifth trench gate.

7. The semiconductor device of claim 1 , further comprising:
a third high-voltage semiconductor device in the substrate between the first and second trench gates, wherein
a portion of the second region is between the first high-voltage semiconductor device and the third high-voltage semiconductor device.

8. The semiconductor device of claim 1 , wherein the third and fourth trench gates cross the first and second trench gates.

9. The semiconductor device of claim 1 , wherein the emitter is in two portions of the first region.

10. The semiconductor device of claim 9 , wherein
the emitter is in only a part of the two portions of the first region, and
the two portions of the first region are at opposite sides of the first region.

11. A semiconductor device comprising:
a substrate;
a first trench gate structure in the substrate,
the first trench gate structure having a ladder shape; and

first and second regions defined in the substrate,
the first and second regions surrounded by portions of the first trench gate structure,
the first region including a high-voltage semiconductor device,
the high-voltage semiconductor device including a body having a first conduction type and vertical thickness that is less than a vertical thickness of the first trench gate structure,
the high-voltage semiconductor device including an emitter in the body,
the emitter having a second conduction type that is opposite the first conduction type,
the high-voltage semiconductor device including a barrier layer below the body, the barrier layer being the second conduction type, a lower surface of the barrier layer is vertically above a lower surface of the first trench gate structure, and
the second region including a first floating well having the first conduction type and a vertical thickness that is thicker than the vertical thickness of the first trench gate structure, a lower surface of the first floating well is below the lower surface of the first trench gate structure.

12. The semiconductor device of claim 11 , wherein
the first region is one among a plurality of first regions defined in the substrate,
the second region is one among a plurality of second regions defined in the substrate,
the plurality of first regions and the plurality of second regions are alternately arranged, and
the high-voltage semiconductor devices in the plurality of first regions and the first floating wells of the plurality of second regions are alternately repeated with each other.

13. The semiconductor device of claim 12 , wherein
a length direction of the first trench gate structure extends in one direction, and
a length of the second region in the one direction is longer than a length of the first region in the one direction.

14. The semiconductor device of claim 11 , further comprising:
a second trench gate structure in the substrate, wherein
the second trench gate structure has the ladder shape, and
the second trench gate structure is adjacent to the first trench gate structure.

15. The semiconductor device of claim 14 , further comprising:
a third region defined in the substrate between the first trench gate structure and the second trench gate structure, wherein
the third region includes a second floating well having the first conduction type.

16. The semiconductor device of claim 11 , wherein the emitter is in two portions of the first region.

17. The semiconductor device of claim 16 , wherein
the emitter is in only a part of the two portions of the first region, and
the two portions of the first region are at opposite sides of the first region.

18. A semiconductor device comprising:
a substrate;
a first repetition unit in the substrate,
the first repetition unit including first and second trench gates extending long in one direction,
the first repetition unit including third and fourth trench gates connecting the first and second trench gates with each other,
the first repetition unit including a first region that is defined in the substrate by the first to fourth trench gates and surrounded by the first to fourth trench gates,
the first region including a plurality of first high-voltage semiconductor devices,
the first repetition unit including a second region defined in the substrate,
the second region being in surface contact with the first region, and

the second region including a plurality of first floating wells having a first conduction type; and
a second repetition unit in the substrate,
the second repetition unit including a plurality of second high-voltage semiconductor devices and a plurality of second floating wells,
the second floating wells having the first conduction type, and
a layout and structure of the first repetition unit being different than a layout and structure of the second repetition unit.

19. The semiconductor device of claim 18 , wherein a width ratio of one of the plurality of first high-voltage semiconductor devices to one of the plurality of first float

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Nam Young

Classifications

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D12/415

  having edge termination structures · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D62/142

  Anode regions of thyristors or collector regions of gated bipolar-mode devices · CPC title

• H10D84/641

  Combinations of only vertical BJTs (vertical complementary BJTs H10D84/673) · CPC title