Method and structure for enabling high aspect ratio sacrificial gates

Patent metadata

Field	Value
Publication number	US-9318574-B2
Application number	US-201414307986-A
Country	US
Kind code	B2
Filing date	Jun 18, 2014
Priority date	Jun 18, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a sacrificial gate stack over a surface of a substrate;
providing a plurality of hard mask structures on a topmost surface of said sacrificial gate stack, wherein an anchoring element is disposed over segments of each hard mask structure;
patterning said sacrificial gate stack into a plurality of sacrificial gate structures utilizing said plurality of hard mask structures and said anchoring element as an etch mask;
removing each hard mask structure to expose a sacrificial gate cap portion of each sacrificial gate structure, wherein end segments of each sacrificial gate cap portion are connected to a sacrificial gate cap anchoring portion;
forming a dielectric spacer comprising a first dielectric material on sidewalls of each of said sacrificial gate structures and sidewalls of said sacrificial gate cap anchoring portion;
forming a planarization dielectric layer laterally surrounding each of said sacrificial gate structures, wherein said planarization dielectric layer has a topmost surface that is coplanar with a topmost surface of each of said sacrificial gate structures; and
removing each sacrificial gate cap anchoring portion to form a spacer cavity.

2. The method of claim 1 , further comprising forming a second dielectric material in said spacer cavity and along end segments of each sacrificial gate structure, wherein said second dielectric material comprises a different material than the first dielectric material of said dielectric spacer.

3. The method of claim 2 , further comprising removing each of said sacrificial gate structures and replacing the same with a functional gate structure.

4. The method of claim 3 , wherein said removing said sacrificial gate structure comprises a recessed etch.

5. The method of claim 3 , wherein said functional gate structure is formed by depositing a blanket layer of a gate dielectric material; and depositing a blanket layer of a gate conductor material on said blanket layer of gate dielectric material.

6. The method of claim 5 , further comprising depositing a blanket layer of a gate gap material on said blanket layer of gate conductor material.

7. The method of claim 1 , wherein said anchoring element is formed by depositing a layer of a masking material and patterning the layer of masking material by lithography and etching.

8. The method of claim 1 , wherein said forming said sacrificial gate stack comprising first depositing a sacrificial gate dielectric, second depositing a sacrificial gate material on said sacrificial gate dielectric, and third depositing a sacrificial gate cap on said sacrificial gate material.

9. The method of claim 1 , wherein each of said sacrificial gate structure has a height from 50 nm to 200 nm, and a width from 5 nm to 30 nm.

10. The method of claim 1 , wherein said sacrificial gate stack straddles a semiconductor fin that extends upward from a surface of said substrate.

11. The method of claim 1 , wherein said substrate includes at least one semiconductor fin, and said sacrificial gate structure straddles said at least one semiconductor fin.

12. The method of claim 11 , wherein said at least one semiconductor fin is formed by a sidewall image transfer process.

13. The method of claim 11 , wherein said dielectric spacer has a bottommost surface contacting a portion of said at least one semiconductor fin.

14. The method of claim 13 , further comprising forming epitaxial semiconductor material portions on other portions of said at least one semiconductor fin.

15. The method claim 14 , further comprising:
forming a second dielectric material in said spacer cavity and along end segments of each sacrificial gate structure, wherein said second dielectric material comprises a different material than the first dielectric material of said dielectric spacer; and
removing each of said sacrificial gate structures and replacing the same with a functional gate structure.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Jung Ryan O
• Lie Fee Li
• Shearer Jeffrey C
• Sporre John R
• Teehan Sean

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D64/01328

  by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title