Wafer level light-emitting diode array

Patent metadata

Field	Value
Publication number	US-9318529-B2
Application number	US-201514722011-A
Country	US
Kind code	B2
Filing date	May 26, 2015
Priority date	Sep 7, 2012
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes.

First claim

The invention claimed is:

1. A light emitting diode array, comprising:
a substrate;
light emitting diodes positioned over the substrate, each light emitting diode including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer;
lower electrodes disposed over the second semiconductor layer of corresponding light emitting diodes;
a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; and
upper electrodes formed over the first interlayer insulating layer and electrically connected to the first semiconductor layer of corresponding light emitting diodes through the first via hole structures;
wherein the first via hole structure of each light emitting diode is disposed in parallel with one side of the corresponding second semiconductor layer, and
wherein the first interlayer insulating layer is disposed to form second via hole structures exposing a portion of the lower electrodes of corresponding light emitting diodes,
wherein the first via hole structure of a given light emitting diode includes a pair of via holes disposed near edges of the given light emitting diode and a connection part connecting the pair of via holes, and one of the pair of via holes is spaced apart by a predetermined distance from at least one of the second via holes.

2. The light emitting diode array of claim 1 , wherein the first via hole structure has a dumbbell shape, a rectangular shape, or a rectangular shape with round corners.

3. The light emitting diode array of claim 1 , wherein the first via hole structure has a length proportional to a length of a longer side of the second semiconductor layer.

4. The light emitting diode array of claim 1 , wherein the first via hole structure for at least one of the light emitting diodes is disposed in a middle region of the corresponding second semiconductor layer.

5. The light emitting diode array of claim 1 , wherein the first via hole structure has a length ranging from no less than 30% to less than 100% of a length of one side of the second semiconductor layer.

6. The light emitting diode array of claim 1 , wherein at least one of the upper electrodes is electrically connected to a second semiconductor layers of corresponding light emitting diodes, and
at least one of the upper electrodes is insulated from the second semiconductor layers of the corresponding light emitting diodes.

7. The light emitting diode array of claim 6 , wherein at least one of the upper electrodes is electrically connected to the second semiconductor layer of the corresponding light emitting diodes through the exposed portions of the lower electrodes.

8. The light emitting diode array of claim 1 , further comprising:
a second interlayer insulating layer covering the upper electrodes,
wherein the second interlayer insulating layer is disposed to form third via hole structures exposing a portion of the corresponding lower electrodes and a portion of the corresponding upper electrodes.

9. The light emitting diode array of claim 8 , wherein at least two of the third via hole structures are symmetrical with respect to the corresponding first via hole structures in a given light emitting diode.

10. The light emitting diode array of claim 8 , wherein the third via hole structures are spaced apart by a predetermined distance from a portion of the corresponding first via hole structure in a given light emitting diode.

11. The light emitting diode array of claim 8 , further comprising:
first and second pads positioned over the second interlayer insulating layer,
wherein the light emitting diodes are connected in series by the upper electrodes, and
the first pad is connected to the exposed portion of the corresponding lower electrodes and the second pad is connected to the exposed portion of the corresponding upper electrodes.

12. The light emitting diode array of claim 1 , wherein the upper electrodes include ohmic contact layers providing ohmic-contacts with the first semiconductor layers.

13. The light emitting diode array of claim 12 , wherein the upper electrodes further include reflective layers positioned over the ohmic contact layers.

14. The light emitting diode array of claim 1 , wherein each of the lower electrodes includes a reflective layer.

15. The light emitting diode array of claim 1 , wherein at least one of the upper electrodes occupies an area no less than 30% and less than 100% of an entire area of the light emitting diode array.

16. The light emitting diode array of claim 1 , wherein at least one of the upper electrodes has a length or a width greater than that of the corresponding light emitting diode.

17. A light emitting diode array, comprising:
a substrate;
light emitting units respectively disposed in a first region and a second region, each light emitting unit including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein the light emitting units in the first and second regions are disposed to form first via structures to expose a portion of the corresponding first semiconductor layers;
lower electrodes disposed over the light emitting units in the first region and the second region except the exposed portion of the first semiconductor layer;
interlayer insulation layers disposed over the lower electrodes to form second via structures to expose a portion of the exposed portion of the first semiconductor layer, wherein the interlayer insulating layers are further disposed to expose a portion of the lower electrodes; and
upper electrodes disposed over the interlayer insulation layers, wherein one of the upper electrodes is disposed in the first region to electrically connect the first semiconductor layer of the corresponding light emitting unit in the first region to the second semiconductor layer of the corresponding light emitting unit in the second region, wherein the first via structure of a given light emitting unit includes a pair of via holes disposed near edges of the given light emitting unit and a connection part connecting the pair of via holes, and one of the pair of via holes is spaced apart by a predetermined distance from at least one of the second via structures.

18. The light emitting diode array of claim 17 ,
wherein at least one of the first via structures includes a pair of holes disposed at ends of the at least one of the first via structures and a connection part connecting the pair of holes.

19. The light emitting diode array of claim 17 ,
wherein the first region and the second region are spaced apart and the upper electrodes are spaced apart to shield spaces between the first region and the second region.

Assignees

• Seoul Viosys Co Ltd

Inventors

• Jang Jong Min
• Chae Jong Hyeon
• Lee Joon Sup
• Suh Daewoong
• Kim Hyun A
• Roh Won Young
• Kang Min Woo

Classifications

• H10H20/819

  characterised by their shape, e.g. curved or truncated substrates · CPC title

• H10H20/84

  Coatings, e.g. passivation layers or antireflective coatings · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/856

  Reflecting means · CPC title