Method for manufacturing solid-state image sensor

Patent metadata

Field	Value
Publication number	US-9318525-B2
Application number	US-201414449299-A
Country	US
Kind code	B2
Filing date	Aug 1, 2014
Priority date	Sep 3, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A first pixel includes a first charge accumulation portion of a first conductivity type in a first region. A second pixel includes a second charge accumulation portion of the first conductivity type in a second region and a semiconductor region of a second conductivity type in a third region. Impurities of the second conductivity type are doped in the third region and the impurities of the second conductivity type are doped in at least the second region to generate a first difference between quantities of doping the impurities of the second conductivity type in the first and second regions. Impurities are doped in the first and second regions to reduce a second difference, caused by the first difference, between net quantities of doping impurities of the first conductivity type in the first and second regions.

First claim

What is claimed is:

1. A method for manufacturing a solid-state image sensor including a first pixel and a second pixel in a semiconductor substrate,
the first pixel including a first charge accumulation portion of a first conductivity type in a first region of the semiconductor substrate, and
the second pixel including a second charge accumulation portion of the first conductivity type in a second region of the semiconductor substrate, and a semiconductor region of a second conductivity type in a third region of the semiconductor substrate, the second conductivity type being different from the first conductivity type,
the method comprising the steps of:
forming the first charge accumulation portion and the second charge accumulation portion; and
forming the semiconductor region,
wherein in the step of forming the semiconductor region, impurities of the second conductivity type are doped in the third region, and the impurities of the second conductivity type are doped in at least the second region such that a first difference is generated between a quantity of doping the impurities of the second conductivity type in the first region, and a quantity of doping the impurities of the second conductivity type in the second region, and
in the step of forming the first charge accumulation portion and the second charge accumulation portion, impurities are doped in the first region and the second region to reduce a second difference between a net quantity of doping impurities of the first conductivity type in the first region, and a net quantity of doping impurities of the first conductivity type in the second region.

2. The method according to claim 1 , further comprising the step of forming a buried layer of the second conductivity type of the semiconductor substrate at a position deeper than the first charge accumulation portion and the second charge accumulation portion,
wherein the first pixel is a pixel configured to receive a light in a first wavelength range, and the second pixel is a pixel configured to receive a light in a second wavelength range, a central wavelength in the second wavelength range being shorter than a central wavelength in the first wavelength range, and
the third region is positioned between the second region and the buried layer.

3. The method according to claim 2 , wherein the step of forming the first charge accumulation portion and the second charge accumulation portion includes the steps of:
doping the impurities of the first conductivity type simultaneously in the first region and the second region; and
doping the impurities of the second conductivity type in the first region out of the first region and the second region.

4. The method according to claim 2 , wherein the step of forming the first charge accumulation portion and the second charge accumulation portion includes the steps of:
doping the impurities of the first conductivity type simultaneously in the first region and the second region; and
doping the impurities of the first conductivity type in the second region out of the first region and the second region.

5. The method according to claim 3 , wherein a mask is commonly used in the step of forming the semiconductor region, and the step of doping the impurities of the first conductivity type in the second region out of the first region and the second region.

6. The method according to claim 2 , wherein the step of forming the first charge accumulation portion and the second charge accumulation portion includes the steps of:
doping the impurities of the first conductivity type in the first region out of the first region and the second region; and
doping the impurities of the first conductivity type in the second region out of the first region and the second region.

7. The method according to claim 1 , wherein the semiconductor region includes a surface exposed on a surface of the semiconductor substrate, and a contact plug is connected to the exposed surface.

8. The method according to claim 7 , wherein the step of forming the first charge accumulation portion and the second charge accumulation portion includes the steps of:
doping the impurities of the first conductivity type simultaneously in the first region and the second region; and
doping the impurities of the first conductivity type in the second region out of the first region and the second region.

9. The method according to claim 7 , wherein the step of forming the first charge accumulation portion and the second charge accumulation portion includes the steps of:
doping the impurities of the first conductivity type in the first region out of the first region and the second region; and
doping the impurities of the first conductivity type in the second region out of the first region and the second region.

10. The method according to claim 7 , wherein the step of forming the first charge accumulation portion and the second charge accumulation portion includes the steps of:
doping the impurities of the first conductivity type simultaneously in the first region and the second region; and
doping the impurities of the second conductivity type in the first region out of the first region and the second region.

11. The method according to claim 1 , wherein both of the impurities of the first conductivity type and the impurities of the second conductivity type are doped into at least one of the first region and the second region through the step of forming the first charge accumulation portion and the second charge accumulation portion and the step of forming the semiconductor region.

12. The method according to claim 1 , wherein the step of forming the semiconductor region includes forming a mask covering the first region and having an opening corresponding to the third region.

13. The method according to claim 1 , wherein the step of forming the first charge accumulation portion and the second charge accumulation portion includes forming a mask covering one of the first region and the second region and having an opening corresponding to another one of the first region and the second region.

14. The method according to claim 1 , wherein the solid-state image sensor includes a surface region of the second conductivity type on the first accumulation region and the second accumulation regions, and wherein the method further comprises a step of forming the surface region.

15. A method for manufacturing a solid-state image sensor including, in a semiconductor substrate, a first pixel configured to receive a light in a first wavelength range, and a second pixel configured to receive a light in a second wavelength range, a central wavelength in the second wavelength range being shorter than a central wavelength in the first wavelength range,
the first pixel including a first charge accumulation portion of a first conductivity type in a first region of the semiconductor substrate,
the second pixel including a second charge accumulation portion of the first conductivity type in a second region of the semiconductor substrate, and a semiconductor region of a second conductivity type in a third region of the semiconductor substrate, the second conductivity type being different from the first conductivity type,
the manufacturing method comprising the steps of:
forming the first charge accumulation portion and the second charge accumulation portion;
forming a buried layer of the second conductivity type of the semiconductor substrate at a position deeper than the first charge accumulation portion and the second charge accumulation portion; and
forming the semiconductor region of the semiconductor substrate between th

Assignees

• Canon Kk

Inventors

• Itoh Hideyuki

Classifications

• H10F39/8063

  Microlenses · CPC title

• H10F39/807

  Pixel isolation structures · CPC title

• H10F39/182

  Colour image sensors · CPC title

• H10F39/014 Primary

  of CMOS image sensors · CPC title

• H01L27/14627

  Electricity · mapped topic