Thin film transistor and display device

Patent metadata

Field	Value
Publication number	US-9318507-B2
Application number	US-201314416213-A
Country	US
Kind code	B2
Filing date	Aug 30, 2013
Priority date	Aug 31, 2012
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; two or more oxide semiconductor layers that are used as a channel layer; an etch stopper layer for protecting the surfaces of the oxide semiconductor layers; a source-drain electrode; and a gate insulator film interposed between the gate electrode and the channel layer. The metal elements constituting an oxide semiconductor layer that is in direct contact with the gate insulator film are In, Zn and Sn. The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.

First claim

The invention claimed is:

1. A thin film transistor, comprising:
a gate electrode,
an oxide semiconductor layer comprising at least a first and a second oxide semiconductor layer,
an etch stopper layer,
a source-drain electrode, and
a gate insulator film,
wherein
the oxide semiconductor layer is configured to be a channel layer;
the etch stopper layer is configured to protect a surface of the oxide semiconductor layer;
the gate insulator film is interposed between the gate electrode and the channel layer;
the first oxide semiconductor layer is in direct contact to the gate insulator film and satisfies the following expressions:
15≦[In]≦35, 50≦[Zn]≦60, 15≦[Sn]≦30

where [In], [Zn], and [Sn] represent a content of each element in atomic % relative to a total content of all metal elements in the first oxide semiconductor layer;
a hydrogen concentration in the gate insulator film in direct contact to the first oxide semiconductor layer is 4 atomic % or lower; and
the second oxide semiconductor layer is in direct contact to the source-drain electrode and satisfies the following expressions:
10≦[In]≦20, 30≦[Zn]≦40, 5≦[Sn]≦15, and 35≦[Ga]≦50

where [In], [Zn], [Sn], and [Ga] represent a content of each element in atomic % relative to a total content of all metal elements in the second oxide semiconductor layer.

2. The thin film transistor according to claim 1 , wherein
the gate insulator film is a single layer structure or a laminate structure comprising two or more layers;
in case of the laminate structure, the hydrogen concentration is 4 atomic % or less in a layer which is in direct contact to the first oxide semiconductor layer.

3. A display device, comprising
the thin film transistor according to claim 1 .

4. The thin film transistor according to claim 1 , wherein the hydrogen concentration in the gate insulator film in direct contact to the first oxide semiconductor layer is 3.5 atomic % or lower.

5. The thin film transistor according to claim 1 , wherein the hydrogen concentration in the gate insulator film in direct contact to the first oxide semiconductor layer is 3 atomic % or lower.

6. The thin film transistor according to claim 1 , wherein the hydrogen concentration in the gate insulator film in direct contact to the first oxide semiconductor layer is 0.667 atomic % or more.

Assignees

• Kobe Steel Ltd

Inventors

• Miki Aya
• Morita Shinya
• Goto Hiroshi
• Tao Hiroaki
• Kugimiya Toshihiro

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title