Method for electronic circuit assembly on a paper substrate

Patent metadata

Field	Value
Publication number	US-9318466-B2
Application number	US-201414471620-A
Country	US
Kind code	B2
Filing date	Aug 28, 2014
Priority date	Aug 28, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate.

First claim

What is claimed is:

1. A method comprising:
integrating one or more passive circuit components on a first surface of a substrate; and
interconnecting one or more integrated circuit (IC) dies on a second surface of the substrate to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces,
wherein the first and second surfaces are opposite surfaces of the substrate, and
wherein the substrate is formed from a carbon-based material different from silicon (Si) and FR4 and which has a coefficient of thermal expansion (CTE) matched to that of Si, and by depositing alumina or a multilayer dielectric that has low permeability to oxygen and moisture on a paper substrate, by atomic layer deposition (ALD).

2. The method of claim 1 , wherein the substrate has a CTE from 1 to 11 ppm/° C.

3. The method of claim 1 , wherein the substrate has a thickness from 25 to 300 microns (μm).

4. The method of claim 1 , further comprising:
forming one or more openings in the substrate;
forming a conformal dielectric layer on all exposed surfaces of the substrate; and
forming the one or more metal-filled vias by filling the one or more openings with solder, tungsten (W), copper (Cu), silver (Ag), titanium (Ti), or other metal-based paste.

5. The method of claim 4 , comprising forming the one or more openings by mechanical punching, laser drilling, or chemical etching.

6. The method of claim 4 , comprising filling the openings by:
performing a first squeegee operation over the first surface of the substrate; and
performing a second squeegee operation over the second surface of the substrate,
wherein the openings in the substrate are utilized as a stencil.

7. The method of claim 1 , comprising integrating the one or more passive circuit components on the first surface of the substrate by:
patterning a metal layer formed on the first surface of the substrate;
forming an insulating layer on the patterned metal layer and on exposed surfaces of the first surface of the substrate; and
forming the one or more passive circuit components in the insulating layer at the patterned metal layer.

8. The method of claim 1 , comprising mounting the one or more IC dies on the second surface of the substrate using one or more solder balls at the one or more metal-filled vias.

9. A method comprising:
forming one or more openings in a substrate by mechanical punching, laser drilling, or chemical etching;
forming a conformal dielectric layer on all exposed surfaces of the substrate;
filling the one or more openings with solder, tungsten (W), copper (Cu), titanium (Ti), silver (Ag) or other metal-based paste, to form one or more metal filled vias;
forming a patterned metal layer on the conformal dielectric layer on one side of the substrate;
forming an insulating layer on the one side of the substrate over the patterned metal layer;
integrating one or more passive circuit components in the insulating layer on the patterned metal layer;
forming one or more solder balls on another side of the substrate at the one or more metal-filled vias; and
mounting one or more integrated circuit (IC) dies on the one or more solder balls,
wherein the one side and the another side correspond to opposite surfaces of the substrate, and
wherein the substrate is formed by depositing alumina or other dielectric that has low permeability to oxygen and moisture on a paper substrate by atomic layer deposition (ALD).

10. The method of claim 9 , comprising forming the substrate from a carbon-based material different from silicon (Si) and FR4 and having a coefficient of thermal expansion (CTE) matched to that of Si.

Assignees

• Globalfoundries Inc

Inventors

• Chadda Saket
• Alapati Ramakanth
• Beece Adam

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title