Methods of fabricating semiconductor chip solder structures

Patent metadata

Field	Value
Publication number	US-9318457-B2
Application number	US-201514818621-A
Country	US
Kind code	B2
Filing date	Aug 5, 2015
Priority date	Aug 30, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.

First claim

What is claimed is:

1. An apparatus, comprising:
a semiconductor chip including a layer of copper, the copper layer having a first preselected volume; and
a layer of a metallic material on the copper layer, the layer of metallic material having a second preselected volume, the first and second metallic materials operable to convert into a solder bump upon reflow with a desired ratio of copper to the layer of metallic material, the desired ratio being based on the first preselected volume and the second preselected volume.

2. The apparatus of claim 1 , wherein the solder bump is substantially lead-free.

3. The apparatus of claim 1 , comprising a circuit board coupled to the semiconductor chip.

4. The apparatus of claim 1 , wherein the metallic material is substantially lead-free.

5. The apparatus of claim 1 , comprising an underbump metallization structure on the semiconductor chip and in ohmic contact with the copper layer and a polymer layer over the underbump metallization structure.

6. The apparatus of claim 1 , comprising a polymer layer on the semiconductor chip and an underbump metallization structure at least partially over the polymer layer and in ohmic contact with the copper layer.

7. The apparatus of claim 1 , comprising an electronic device coupled to the semiconductor chip.

8. The apparatus of claim 1 , comprising a circuit board coupled to the semiconductor chip.

9. The apparatus of claim 8 , wherein the circuit board comprises a semiconductor chip package substrate.

10. An apparatus, comprising:
a semiconductor chip including solder bump; and
whereby the solder bump being formed by depositing a layer of copper on the semiconductor chip, the copper layer having a first preselected volume, depositing a layer of a metallic material on the copper layer, the layer of metallic material having a second preselected volume, and reflowing the copper layer and the layer of metallic material to convert them into a solder bump with a desired ratio of copper to the layer of metallic material, the desired ratio being based on the first preselected volume and the second preselected volume.

11. The apparatus of claim 10 , wherein the solder bump is substantially lead-free.

12. The apparatus of claim 10 , wherein the copper layer is deposited by sputtering.

13. The apparatus of claim 10 , wherein the layer of the metallic material is deposited by plating.

14. The apparatus of claim 10 , comprising a polymer layer on the semiconductor chip with a first opening, at least a portion of the copper layer being in the first opening.

15. The apparatus of claim 10 , comprising an underbump metallization structure on the semiconductor chip below the copper layer and a polymer layer over the underbump metallization structure.

16. The apparatus of claim 10 , comprising a polymer layer on the semiconductor chip and an underbump metallization on the semiconductor chip, the underbump metallization structure being at least partially over the polymer layer.

17. The apparatus of claim 10 , comprising a circuit board coupled to the semiconductor chip.

18. The apparatus of claim 17 , wherein the circuit board comprises a semiconductor chip package substrate.

19. An apparatus, comprising:
a semiconductor chip including a layer of copper, the copper layer having a first preselected volume; and
a layer of tin on the copper layer, the layer of tin having a second preselected volume, the copper layer and the tin layer being operable to convert into a solder bump upon reflow with a desired ratio of copper to tin, the desired ratio being based on the first preselected volume and the second preselected volume.

20. The apparatus of claim 19 , comprising a polymer layer on the semiconductor chip and an underbump metallization on the semiconductor chip, the underbump metallization structure being at least partially over the polymer layer.

Assignees

• Topacio Roden R
• Mclellan Neil
• Ati Technologies Ulc
• Advanced Micro Devices Inc

Inventors

• Topacio Roden R
• Mclellan Neil

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/01955

  by using masks · CPC title