Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

Patent metadata

Field	Value
Publication number	US-9318430-B2
Application number	US-201514602559-A
Country	US
Kind code	B2
Filing date	Jan 22, 2015
Priority date	Apr 12, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

First claim

The invention claimed is:

1. A method of forming an array of cross-point memory cells, comprising:
forming a stack of horizontally extending and vertically overlapping dielectric features, the stack comprising a primary portion and an end portion, at least some of the dielectric features extending farther in the horizontal direction in the end portion moving deeper into the stack in the end portion;
forming openings through the dielectric features in the primary portion and in the end portion;
lining the openings with first material;
lining the first material-lined openings with programmable material;
filling remaining volume of the first and programmable material-lined openings with conductive material;
forming horizontally elongated trenches through the dielectric features to form horizontally elongated and vertically overlapping dielectric lines from dielectric material of the dielectric features, the dielectric lines individually extending from the primary portion into the end portion and individually laterally about sides of both the openings in the primary and end portions;
removing at least some of sacrificial material that is elevationally between the dielectric lines in the primary and end portions laterally between the trenches selectively relative to the dielectric lines and the first material lining in the openings;
after removing at least a portion of the sacrificial material, removing at least a portion of the first material that is elevationally between the dielectric lines to expose laterally outer sidewalls of the programmable material that is elevationally between the dielectric lines; and
replacing at least a portion of the sacrificial material with conductor material that is in electrical connection with the laterally outers sidewalls of the programmable material and to comprise vertically spaced horizontal conductive lines; individual ones of the cross-point memory cells comprising crossing ones of the horizontal conductive lines in the primary portion and conductive material in the openings in the primary portion having the programmable material there-between.

2. The method of claim 1 comprising forming the trenches after the filling.

3. The method of claim 1 wherein the conductive material and the conductor material are of the same composition.

4. The method of claim 1 wherein the conductive material and the conductor material are of different compositions.

5. The method of claim 1 wherein the first material is dielectric.

6. The method of claim 1 wherein the features comprise plates.

7. The method of claim 1 comprising forming the primary portion openings and the end portion openings at the same time.

8. The method of claim 1 comprising forming the primary portion openings and the end portion openings at different times.

9. The method of claim 1 comprising forming at least some of the end portion openings to horizontally overlap ends of individual ones of the features.

10. The method of claim 1 comprising forming the primary portion openings and the end portion openings to have the same horizontal and vertical cross sections.

11. The method of claim 1 comprising forming the primary portion openings and the end portion openings to have at least one of different horizontal cross sections or different vertical cross sections.

12. A method of forming circuitry components, comprising:
forming a stack of horizontally extending and vertically overlapping features, the stack comprising a primary portion and an end portion, at least some of the features extending farther in the horizontal direction in the end portion moving deeper into the stack in the end portion;
forming first structures vertically through the features in the primary portion and forming second structures vertically through the features in the end portion;
removing at least some sacrificial material that is elevationally between material of the features in the primary and end portions to form void spaces elevationally between the horizontally extending and vertically overlapping features; and
forming conductor material within the void space and forming a stack of horizontally extending and vertically overlapping conductive lines from the conductor material.

13. The method of claim 12 comprising forming the conductive material of the conductive lines to horizontally wrap around the first structures.

14. The method of claim 12 comprising forming the first structures to at least initially comprise hollow cylinders.

15. The method of claim 14 comprising forming conductive material to extend vertically within the hollow cylinders.

16. The method of claim 15 wherein the conductive material is formed after forming the conductor material.

17. The method of claim 15 wherein the conductive material is formed before forming the conductor material.

18. A method of forming an array of cross-point memory cells, comprising:
forming a stack of horizontally extending and vertically overlapping dielectric features, the stack comprising a primary portion and an end portion, at least some of the dielectric features extending farther in the horizontal direction in the end portion moving deeper into the stack in the end portion;
forming openings through the dielectric features in the primary portion and in the end portion;
lining the openings with first material;
forming programmable material and conductive material within the first material-lined openings;
forming horizontally elongated trenches through the dielectric features to form horizontally elongated and vertically overlapping dielectric lines from dielectric material of the dielectric features, the dielectric lines individually extending from the primary portion into the end portion and individually laterally about sides of both the openings in the primary and end portions;
removing at least some of sacrificial material that is elevationally between the dielectric lines in the primary and end portions laterally between the trenches selectively relative to the dielectric lines and the first material lining in the openings;
after removing at least a portion of the sacrificial material, removing at least a portion of the first material that is elevationally between the dielectric lines to expose laterally outer sidewalls of the programmable material that is elevationally between the dielectric lines; and
replacing at least a portion of the sacrificial material with conductor material that is in electrical connection with the laterally outers sidewalls of the programmable material and to comprise vertically spaced horizontal conductive lines; individual ones of the cross-point memory cells comprising crossing ones of the horizontal conductive lines in the primary portion and conductive material in the openings in the primary portion having the programmable material there-between.

19. The method of claim 12 comprising forming the conductive lines to comprise conductive lines of cross-point memory cells.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Lindsay Roger W
• Parat Krishna K

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• G11C2213/75

  Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title