Pop package structure

Patent metadata

Field	Value
Publication number	US-9318407-B2
Application number	US-201314107808-A
Country	US
Kind code	B2
Filing date	Dec 16, 2013
Priority date	Dec 21, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A package on package (PoP) package structure is disclosed, the structure includes at least two layers of carrier boards that are packaged and stacked in sequence, wherein chips are arranged on the bottom side of the carrier boards, a heat sink is arranged on the bottom side of a carrier board other than a layer-1 carrier board, a pad welded to a system board is arranged on the bottom side of the layer-1 carrier board, and a chip on a carrier board other than a top-layer carrier board is surface-mounted onto the heat sink adjacent to the chip. The heat sink increases the heat dissipation area of the chip, enhances the heat dissipation capabilities of the PoP stacked packages massively, breaks the bottleneck of the high-density integration and miniaturization of the PoP stacked packages, and enhances the packaging density of the PoP stacked packages.

First claim

What is claimed is:

1. A package on package (PoP) package structure, comprising:
a layer- 1 carrier board comprising a pad arranged on a bottom side of the layer- 1 carrier board that is configured to weld the PoP package structure to a system board;
a top-layer carrier board;
at least one other carrier board positioned between the layer- 1 carrier board and the top-layer carrier board, wherein the layer- 1 carrier board, the top-layer carrier board, and the at least one other carrier board are packaged and stacked in sequence;
a heat sink that is arranged on a bottom side of the top-layer carrier board and/or a bottom side of the at least one other carrier board, wherein the heat sink includes an extension part that extends out of the top-layer carrier board or the at least one other carrier board and that bends upward or downward; and
a chip on the layer- 1 carrier board and/or on the at least one other carrier board that is surface-mounted onto the heat sink adjacent to the chip.

2. The PoP package structure according to claim 1 , wherein the heat sink does not contact an electrical connection region on the top-layer carrier board or the at least one other carrier board that is connected to the heat sink.

3. The PoP package structure according to claim 2 , wherein the heat sink comprises a rectangular shape, an I-shape, a crossshape, or an irregular shape.

4. The PoP package structure according to claim 1 , wherein a thermal interface material is arranged between the heat sink and the chip.

5. The PoP package structure according to claim 1 , wherein a second heat sink is bonded onto a chip on the top-layer carrier board through a thermally conductive adhesive.

6. The PoP package structure according to claim 1 , wherein a heat dissipating copper plate is arranged on the heat sink.

7. The PoP package structure according to claim 1 , wherein heat dissipating holes are opened on the heat sink.

8. The PoP package structure according to claim 1 , wherein a heat dissipating copper sheet is arranged on a sidewall of the top-layer carrier board or the at least one other carrier board where the heat sink is arranged.

9. The PoP package structure according to claim 1 , wherein the heat sink comprises a copper sheet that is directly press-fit into the top-layer carrier board or the at least one other carrier board where the heat sink is arranged and is etched into a corresponding pattern.

10. The PoP package structure according to claim 1 , wherein any two adjacent layers of the layer- 1 carrier board, the top-layer carrier board, and the at least one other carrier board are connected through a PoP pad.

11. The PoP package structure according to claim 10 , wherein the PoP pad is isolated from the heat sink.

12. A package on package (PoP) package structure, comprising:
a first carrier board;
a second carrier board that is packaged and stacked in sequence with the first carrier board;
a heat sink that is arranged on a bottom side of the second carrier board; and
a chip that is arranged on the first carrier board and that is surface-mounted to the heat sink,
wherein the heat sink comprises an I-shape or a cross-shape, and
wherein the heat sink comprises an extension part that extends out of the second carrier board and that bends upward or downward.

13. The PoP package structure according to claim 12 , wherein the heat sink comprises outward portions that extend out from the first carrier board and the second carrier board, and wherein the outward portions are at an angle with respect to the first carrier board and the second carrier board.

14. The PoP package structure according to claim 12 , wherein a second heat sink is bonded onto a chip on the top-layer carrier board through a thermally conductive adhesive.

15. The PoP package structure according to claim 12 , wherein a thermal interface material is arranged between the heat sink and the chip.

16. The PoP package structure according to claim 12 , wherein a heat dissipating copper plate is arranged on the heat sink.

17. The PoP package structure according to claim 12 , wherein heat dissipating holes are opened on the heat sink.

18. The PoP package structure according to claim 12 , wherein the first carrier board and the second carrier board are connected through a PoP pad.

Assignees

• Huawei Tech Co Ltd

Inventors

• Liu Weifeng
• Ye Yuming
• Xiang Zhao
• Xu Zhi

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/721

  of bump connectors · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title