Integrated circuit having plural transistors with work function metal gate structures

Patent metadata

Field	Value
Publication number	US-9318389-B1
Application number	US-201414520342-A
Country	US
Kind code	B1
Filing date	Oct 22, 2014
Priority date	Sep 26, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

First claim

What is claimed is:

1. An integrated circuit having plural transistors with different threshold voltages, comprising:
a substrate;
a first transistor with a first metal gate disposed on the substrate, wherein the first metal gate comprises a first bottom barrier layer, a first work function metal (WFM) layer and a first metal layer;
a second transistor with a second metal gate disposed on the substrate, wherein the second metal gate comprises a second bottom barrier layer, a second WFM layer and a second metal layer; and
a third transistor with a third metal gate disposed on the substrate, wherein the third metal gate comprises a third bottom barrier layer, a third WFM layer and a third metal layer, wherein the first transistor, the second transistor and the third transistor have the same conductive type, and a nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

2. The integrated circuit according to claim 1 , wherein a titanium concentration of the first bottom barrier layer<a titanium concentration of the second bottom barrier layer<a titanium concentration of the third bottom barrier layer.

3. The integrated circuit according to claim 1 , wherein a thickness of the first bottom barrier layer<a thickness of the second bottom barrier layer<a thickness of the third bottom barrier layer.

4. The integrated circuit according to claim 1 , wherein a threshold voltage of the first transistor>a threshold voltage of the second transistor>a threshold voltage of the third transistor.

5. The integrated circuit according to claim 1 , wherein the nitrogen concentration in the first bottom barrier layer, the nitrogen concentration in the second bottom barrier layer, and the nitrogen concentration in the third bottom barrier layer increase from a side near the substrate toward a side far from the substrate.

6. The integrated circuit according to claim 1 , wherein the nitrogen concentration of the first bottom barrier layer, the nitrogen concentration of the second bottom barrier layer, and the nitrogen concentration of the third bottom barrier layer decrease from a side near the substrate toward a side far from the substrate.

7. The integrated circuit according to claim 1 , wherein the first transistor, the second transistor and the third transistor are N type transistors.

8. The integrated circuit according to claim 1 , wherein,
the first transistor further comprises a first upper bottom barrier layer disposed between the first bottom barrier layer and the first WFM layer;
the second transistor further comprises a second upper bottom barrier layer disposed between the second bottom barrier layer and the second WFM layer; and
the third transistor further comprises a third upper bottom barrier layer disposed between the third bottom barrier layer and the third WFM layer, wherein a nitrogen concentration of the first upper bottom barrier layer>a nitrogen concentration of the second upper bottom barrier layer>a nitrogen concentration of the third upper bottom barrier layer.

9. The integrated circuit according to claim 8 , wherein a tantalum concentration of the first upper bottom barrier layer<a tantalum concentration of the second upper bottom barrier layer>a tantalum concentration of the third upper bottom barrier layer.

Assignees

• United Microelectronics Corp

Inventors

• Yang Chih-Wei
• Liu Yu-Feng
• Ke Jian-Cun
• Hsu Chia-Fu
• Yang Yu-Ru
• Liou En-Chiuan

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title