Methods of removing fins for finfet semiconductor devices

US9318342B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9318342-B2
Application numberUS-201514811987-A
CountryUS
Kind codeB2
Filing dateJul 29, 2015
Priority dateMar 3, 2014
Publication dateApr 19, 2016
Grant dateApr 19, 2016

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Abstract

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One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: forming a trench patterning hard mask layer above a surface of a semiconductor substrate; performing at least one first etching process through said trench patterning hard mask layer to define a plurality of trenches in said semiconductor substrate to thereby define a plurality of initial fins in said substrate, wherein at least one of said initial fins is a to-be-removed fin; forming a layer of insulating material within said trenc…

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What does patent US9318342B2 cover?
One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on…
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10P50/694. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).