Method for fabricating semiconductor device including nitrided gate insulator

Patent metadata

Field	Value
Publication number	US-9318335-B2
Application number	US-201514685618-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	Sep 1, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A method of fabricating a semiconductor device includes forming an interface layer on a substrate, forming a first gate insulating layer having a first dielectric constant on the interface layer, forming a second gate insulating layer having a second dielectric constant smaller than the first dielectric constant on the first gate insulating layer, annealing the substrate, nitriding a resultant of the annealed first and second gate insulating layers to form a nitrided gate insulator, forming a work function control layer on the nitride gate insulator, and forming a metal gate electrode on the work function control layer. At least one of the work function control layer and the metal gate electrode is of or includes aluminum (Al).

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming an interface layer on a substrate;
forming a first gate insulating layer having a first dielectric constant on the interface layer;
forming a second gate insulating layer having a second dielectric constant smaller than the first dielectric constant on the first gate insulating layer;
annealing the substrate;
nitriding the first and second gate insulating layers to form a nitride gate insulator;
forming a work function control layer on the nitrided gate insulator; and
forming a metal gate electrode on the work function control layer, and
wherein at least one of the work function control layer and the metal gate electrode comprises aluminum (Al).

2. The method of claim 1 , wherein the interface layer and the second gate insulating layer are formed of the same oxide.

3. The method of claim 1 , wherein the second gate insulating layer is formed of a silicon oxide.

4. The method of claim 3 , wherein the first gate insulating layer is formed of a hafnium oxide.

5. The method of claim 1 , wherein:
the first gate insulating layer is formed by n cycles of an atomic layer deposition process, wherein n is a natural number, and
the second gate insulating layer is formed by m cycles of an atomic layer deposition process, wherein m is a natural number less than n.

6. The method of claim 1 , further comprising:
forming a third gate insulating layer, of the same material as the first gate insulating layer, on the second gate insulating layer; and
forming a fourth gate insulating layer of the same material as the second gate insulating layer on the third gate insulating layer.

7. The method of claim 6 , wherein:
the first gate insulating layer is formed by n cycles of a first atomic layer deposition process, wherein n is a natural number,
the second gate insulating layer is formed by m cycles of a second atomic layer process, wherein m is a natural number less than n,
the third gate insulating layer is formed by m cycles of the first atomic layer deposition process, and
the fourth gate insulating layer is formed by m cycles of the second atomic layer deposition process.

8. The method of claim 1 , wherein the annealing of the substrate includes flash, spike, or laser annealing the substrate at 800to 1200° C.

9. The method of claim 1 , wherein the nitriding of first and second gate insulating layers is carried out in an atmosphere comprising a nitride gas whose pressure is maintained in a range of 100 millitorr to 500 millitorr.

10. The method of claim 1 , further comprising:
forming a capping layer on the first and second gate insulating layers; and
forming a barrier layer on the capping layer, and
wherein the work function control layer is formed on the barrier layer.

11. The method of claim 10 , wherein:
the capping layer is formed of TiN,
the barrier layer is formed of TaN, and
the work function control layer is formed of at least one of TiN and TaN.

12. The method of claim 10 , wherein the forming of the work function control layer includes:
forming a p type work function control layer in first and second regions,
removing the p type work function control layer from the first region, and
forming an n type work function control layer in the first and second regions.

13. The method of claim 1 , further comprising:
forming an interlayer insulating layer and a dummy gate electrode on the substrate; and
exposing the surface of the substrate by removing the dummy gate electrode, and
wherein the interface layer is formed on the exposed surface of the substrate.

14. A method of fabricating a semiconductor device, the method comprising:
forming an interface layer on a substrate;
forming a first gate insulating layer having a first dielectric constant on the interface layer, and
forming a second gate insulating layer having a second dielectric constant smaller than the first dielectric constant and including silicon (Si) on the first gate insulating layer;
annealing the substrate;
nitriding the first and second gate insulating layers after annealing the substrate, in an atmosphere comprising a nitride gas;
forming a work function control layer on the nitrided gate insulating layers; and
forming a metal gate electrode on the work function control layer.

15. The method of claim 14 , further comprising repeating processes used to form the first and second gate insulating layers, respectively, to form at least third and fourth gate insulating layers on the second gate insulating layer.

16. The method of claim 14 , wherein:
the first gate insulating layer is formed of a hafnium oxide, and
the second gate insulating layer is formed of a silicon oxide.

17. The method of claim 14 , wherein at least one of the work function control layer and the metal gate electrode comprises aluminum (Al).

18. A method of fabricating a semiconductor device, the method comprising:
providing a substrate;
forming a first interface layer on the substrate in a first region;
forming a second interface layer, having a width different from that of the first interface layer, on the substrate in the second region;
forming a first gate insulator doped with silicon (Si) on the first interface layer;
forming a second gate insulator doped with silicon (Si) on the second interface layer;
annealing the substrate;
nitriding the first gate insulator so that the first gate insulator has a first nitrogen concentration and nitriding the second gate insulator so that the second gate insulator has a second nitrogen concentration different from the first nitrogen concentration, after the annealing of the substrate;
forming a work function control layer on the first and second gate insulators after nitriding the first and second gate insulators; and
forming a metal gate electrode on the work function control layer.

19. The method of claim 18 , wherein:
the first and second interface layers are formed such that the first interface layer is narrower than the second interface layer, and
the nitiriding is carried out such that the first nitrogen concentration is higher than the second nitrogen concentration.

Assignees

• Kim Weon-Hong
• Song Moon-Kyun
• Lee Min-Joo
• Jung Hyung-Suk
• Samsung Electronics Co Ltd

Inventors

• Kim Weon-Hong
• Song Moon-Kyun
• Lee Min-Joo
• Jung Hyung-Suk

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10D64/01316

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D64/01332 Primary

  Making the insulator · CPC title