Semiconductor devices having low threading dislocations and improved light extraction and methods of making the same

Patent metadata

Field	Value
Publication number	US-9318327-B2
Application number	US-56371206-A
Country	US
Kind code	B2
Filing date	Nov 28, 2006
Priority date	Nov 28, 2006
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Semiconductor device structures are provided that are suitable for use in the fabrication of electronic devices such as light emitting diodes. The semiconductor device structures include a substrate having a roughened growth surface suitable for supporting the growth of an epitaxial region thereon. The device structure can include an epitaxial region having reduced defects and/or improved radiation extraction efficiency on the roughened growth surface of the substrate. The roughened growth surface of the substrate can have an average roughness R a of at least about 1 nanometer (nm) and an average peak to valley height R z of at least about 10 nanometers (nm).

First claim

That which is claimed is:

1. A semiconductor device structure suitable for use in the fabrication of electronic devices such as light emitting diodes, comprising:
a substrate comprising a substantially randomly or irregularly roughened growth surface suitable for supporting the growth of an epitaxial region thereon, wherein the roughened growth surface of said substrate has an average roughness R a of at least about 1 nanometer (nm);
an epitaxial region on said substrate; and
first and second ohmic contacts on opposite sides of said semiconductor device, such that said semiconductor device is a vertical semiconductor device.

2. The semiconductor device structure of claim 1 , wherein the roughened growth surface of said substrate has an average peak to valley height R z of at least about 10 nanometers (nm).

3. The semiconductor device structure of claim 1 , wherein the epitaxial region includes fewer defects as compared to the same epitaxial region on a substantially smooth growth surface of said substrate.

4. The semiconductor device structure of claim 1 , wherein the epitaxial region has a threading dislocation of less than or about 6×10 8 cm −2 .

5. The semiconductor device structure of claim 4 , wherein the epitaxial region has a threading dislocation of less than or about 10 8 cm −2 .

6. The semiconductor device structure of claim 1 , wherein the substrate further comprises a second roughened surface opposite the roughened growth surface.

7. The semiconductor device structure of claim 6 , wherein the second roughened surface of the substrate has an average roughness R a of at least about 1 nanometer (nm).

8. The semiconductor device structure of claim 7 , wherein the second roughened surface of the substrate has an average peak to valley height R z of at least about 10 nanometers (nm).

9. The semiconductor device structure of claim 1 , wherein said substrate comprises a material selected from silicon carbide, aluminum nitride, gallium nitride, silicon, gallium arsenide, gallium phosphide, zinc oxide, and sapphire.

10. The semiconductor device structure of claim 1 , wherein said substrate comprises a conductive substrate.

11. The semiconductor device structure of claim 1 , wherein the substrate comprises silicon carbide (SiC).

12. The semiconductor device structure of claim 1 , wherein the epitaxial region comprises an active region capable of emitting radiation.

13. The semiconductor device structure of claim 12 , wherein the roughened growth surface of the substrate has a roughness sufficient to increase the radiation extraction efficiency of the active region as compared to the radiation extraction efficiency of the same active region on a substantially smooth growth surface.

14. The semiconductor device structure of claim 13 , wherein the active region comprises a Group III nitride.

15. The semiconductor device structure of claim 14 , wherein the Group III nitride is selected from the group consisting of A 1 N, GaN, InN, A 1 GaN, AlInN, InGaN, and AlInGaN.

16. The semiconductor device structure of claim 15 , wherein Group III nitride comprises InGaN.

17. The semiconductor device structure of claim 12 , further comprising an n-type layer along a first surface of the active region and a p-type layer on a second opposing surface of the active region to form a diode region.

18. The semiconductor device structure of claim 17 , wherein each of the n-type layer and the p-type layer comprises a Group III nitride layer.

19. The semiconductor device structure of claim 1 , wherein the epitaxial region includes a buffer layer.

20. A light emitting diode, comprising:
a conductive substrate comprising a substantially randomly or irregularly roughened growth surface suitable for supporting the growth of an epitaxial region thereon, wherein the roughened growth surface of the conductive substrate has an average roughness R a of at least about 1 nanometer (nm);
a diode region comprising an epitaxial region on the growth surface of the conductive substrate; and
a first ohmic layer on a surface of the conductive substrate opposite the diode region and a second ohmic contact on a surface of the diode region opposite the conductive substrate.

21. The light emitting diode of claim 20 , wherein the roughened growth surface of the substrate has an average peak to valley height R z of at least about 10 nanometers (nm).

22. The light emitting diode of claim 20 , wherein the epitaxial region includes fewer defects as compared to the same epitaxial region on a substantially smooth growth surface of said substrate.

23. The light emitting diode of claim 20 , wherein the epitaxial region has a threading dislocation of less than or about 6×10 8 cm −2 .

24. The light emitting diode of claim 23 , wherein the epitaxial region has a threading dislocation of less than or about 10 8 cm −2 .

25. The light emitting diode of claim 20 , wherein the substrate further comprises a second roughened surface opposite the roughened growth surface.

26. The light emitting diode of claim 25 , wherein the second roughened surface of the substrate has an average roughness R a of at least about 1 nanometer (nm).

27. The light emitting diode of claim 26 , wherein the second roughened surface of the substrate has an average peak to valley height R z of at least about 10 nanometers (nm).

28. The light emitting diode of claim 20 , wherein said substrate comprises a material selected from silicon carbide, aluminum nitride, gallium nitride, silicon, gallium arsenide, gallium phosphide, zinc oxide, and sapphire.

29. The light emitting diode of claim 20 , wherein said substrate comprises a conductive substrate.

30. The light emitting diode of claim 20 , wherein the substrate comprises silicon carbide (SiC).

31. The light emitting diode of claim 20 , wherein the diode region comprises a n-type layer, an active region, and a p-type layer.

32. The light emitting diode of claim 31 , wherein each of the n-type layer, the active layer and the p-type layer independently comprises a Group III nitride layer.

33. The light emitting diode of claim 20 , further comprising a reflective layer on a surface of the diode region opposite the substrate.

34. The light emitting diode of claim 33 , further comprising a submount on a surface of the reflective layer opposite the diode region.

35. A method of fabricating a semiconductor device structure suitable for use in the fabrication of electronic devices such as light emitting diodes, comprising:
treating a substrate growth surface suitable for supporting the growth of an epitaxial region thereon to substantially randomly or irregularly roughen the growth surface sufficient to provide a growth surface having an average roughness R a of at least about 1 nanometer (nm);
forming an epitaxial region on the roughened growth surface of the substrate; and
providing first and second ohmic contacts on opposite sides of said semiconductor device, such that said semiconductor device is a vertical semiconductor device.

36. The method of claim 35 , wherein the treating step comprises treating the growth surface of the substrate under conditions sufficient to provide a growth surface having an average peak to valley hei

Assignees

• Bergmann Michael John
• Hansen Jason
• Emerson David Todd
• Haberern Kevin Ward
• Cree Inc

Inventors

• Bergmann Michael John
• Hansen Jason
• Emerson David Todd
• Haberern Kevin Ward

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/2923

  being conductive materials, e.g. metallic silicides · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P14/2914

  Oxides · CPC title

• H10P14/2911

  Arsenides · CPC title