Memory device with secure test mode

Patent metadata

Field	Value
Publication number	US-9318221-B2
Application number	US-201414244000-A
Country	US
Kind code	B2
Filing date	Apr 3, 2014
Priority date	Apr 3, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.

First claim

The invention claimed is:

1. A method, comprising:
in a memory device operating in a testing mode, receiving a vector to be written to the memory device;
writing the vector to the memory device only if the vector belongs to a predefined set of test vectors; and
if the vector does not belong to the set of test vectors, converting the vector to one of the test vectors by selecting a subset of bits of the vector and replacing remaining bits of the vector with periodic replications of the selected subset, and writing the converted vector to the memory device.

2. The method according to claim 1 , wherein in any of the test vectors all the even-order bits equal a first bit value and all the odd-order bits equal a second bit value, and wherein converting the vector comprises selecting, in the vector, a representative even bit and a representative odd bit, replacing the even-order bits of the vector with the representative even bit, and replacing the odd-order bits of the vector with the representative odd bit.

3. The method according to claim 1 , and comprising testing the memory by reading a data word of a previously written test vector, and exposing outside the memory device encoded information about errors in the read data word.

4. The method according to claim 3 , wherein exposing the encoded information comprises exposing a total number of the errors.

5. The method according to claim 3 , wherein exposing the encoded information comprises not exposing true locations of the errors.

6. The method according to claim 5 , wherein not exposing the true locations of the errors comprises shifting even-order and odd-order bits that indicate errors to different respective even-order or odd-order locations.

7. The method according to claim 3 , wherein exposing the encoded information comprises further exposing a true location of a subset of the errors.

8. A memory device, comprising:
a memory; and
a memory controller, which configured to operate in a testing mode, to receive a vector to be written to the memory, to write the vector to the memory only if the vector belongs to a predefined set of test vectors, and, if the vector does not belong to the set of test vectors, to convert the vector to one of the test vectors by selecting a subset of bits of the vector and replacing remaining bits of the vector with periodic replications of the selected subset, and to write the converted vector to the memory.

9. The memory device according to claim 8 , wherein in any of the test vectors, all the even-order bits equal a first bit value and all the odd-order bits equal a second bit value, and wherein the memory controller is configured to select, in the vector, a representative even bit and a representative odd bit, and to replace the even-order bits of the vector with the representative even bit, and to replace the odd-order bits of the vector with the representative odd bit.

10. The memory device according to claim 8 , wherein the memory controller is configured to read a data word of a previously written test vector, and to expose outside the memory device encoded information about errors in the read data word.

11. The memory device according to claim 10 , wherein the memory controller is configured to expose a total number of the errors.

12. The memory device according to claim 10 , wherein the memory controller is configured not to expose true locations of the errors.

13. The memory device according to claim 12 , wherein the memory controller is configured not to expose the true locations of the errors by shifting even-order and odd-order bits that indicate errors to different respective even-order or odd-order locations.

14. The memory device according to claim 10 , wherein the memory controller is configured to further expose a true location of a subset of the errors.

Assignees

• Winbond Electronics Corp
• Winbound Electronics Corp

Inventors

• Tasher Nir
• Kaluzhny Uri
• Weiser Tsachi
• Teper Valery

Classifications

• G11C29/38 Primary

  Response verification devices · CPC title

• G06F11/0769

  Readable error formats, e.g. cross-platform generic formats, human understandable formats · CPC title

• G06F11/26

  Functional testing · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title