Methods for modifying an integrated circuit layout design

Patent metadata

Field	Value
Publication number	US-9317645-B2
Application number	US-201313955300-A
Country	US
Kind code	B2
Filing date	Jul 31, 2013
Priority date	Jul 31, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Methods for modifying a layout design of an integrated circuit are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial circuit layout design comprising a lower metal layer, an upper metal layer, and a first via electrically connecting the lower metal layer to the upper metal layer. The method further includes altering the initial circuit layout design by providing a second via, the second via being in electrical contact with no more than one of the upper metal layer and the lower metal layer, and the second via further being in proximity to the first via. Further, the method includes further altering the initial circuit layout design by providing a subresolution assist feature in proximity to the second via.

First claim

What is claimed is:

1. A method for modifying an integrated circuit layout design, the method comprising:
providing an initial circuit layout design comprising a lower metal layer, an upper metal layer, and a first via electrically connecting the lower metal layer to the upper metal layer;
altering, by using a computer, the initial circuit layout design by providing a second via, the second via being in electrical contact with no more than one of the upper metal layer and the lower metal layer, the second via further being in proximity to the first via; and
further altering, by using the computer, the initial circuit layout design by providing a subresolution assist feature in proximity to the second via,
wherein the altering the initial circuit layout design is used to manufacture integrated circuits or wherein the altering the initial circuit layout design is provided to a fabrication facility to fabricate integrated circuits.

2. The method of claim 1 , wherein the second via is in electrical contact with neither the upper metal layer nor the lower metal layer.

3. The method of claim 1 , wherein the second via is in electric contact with the lower metal layer but not the upper metal layer.

4. The method of claim 1 , further comprising photolithographically printing the lower metal layer, the upper metal layer, the first via, and the second via on a semiconductor wafer.

5. The method of claim 1 , further comprising applying a bias to modify the initial circuit layout design.

6. The method of claim 1 , further comprising altering the initial circuit layout design by providing a plurality of vias that are in electrical contact with no more than one of the upper metal layer and the lower metal layer.

7. The method of claim 6 , wherein at least one of the plurality of vias is in electrical contact with neither the upper metal layer nor the lower metal layer and wherein at least one other of the plurality of vias is in electric contact with the lower metal layer but not the upper metal layer.

8. A system for modifying an integrated circuit layout design, the system comprising:
a display device;
a user input device;
a storage device; and
a processor electronically and communicatively coupled to the display device, the user input device, and the storage device and configured to perform the following procedures:
provide an initial circuit layout design comprising a lower metal layer, an upper metal layer, and a first via electrically connecting the lower metal layer to the upper metal layer;
alter the initial circuit layout design, using the processor, by providing a second via, the second via being in electrical contact with no more than one of the upper metal layer and the lower metal layer, the second via further being in proximity to the first via; and
further alter the initial circuit layout design, using the processor, by providing a subresolution assist feature in proximity to the second via,
wherein the altering the initial circuit layout design is used to manufacture integrated circuits or wherein the altering the initial circuit layout design is provided to a fabrication facility to fabricate integrated circuits.

9. The system of claim 8 , wherein the second via is in electrical contact with neither the upper metal layer nor the lower metal layer.

10. The method of claim 8 , wherein the second via is in electric contact with the lower metal layer but not the upper metal layer.

11. The method of claim 8 , wherein the processor is further configured to apply a bias to modify the initial circuit layout design.

12. The method of claim 8 , wherein the processor is further configured to alter the initial circuit layout design by providing a plurality of vias that are in electrical contact with no more than one of the upper metal layer and the lower metal layer.

13. The method of claim 12 , wherein at least one of the plurality of vias is in electrical contact with neither the upper metal layer nor the lower metal layer and wherein at least one other of the plurality of vias is in electric contact with the lower metal layer but not the upper metal layer.

Assignees

• Globalfoundries Inc

Inventors

• Hamouda Ayman

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F2117/06

  Spare resources, e.g. for permanent fault suppression · CPC title

• G03F7/70441

  Optical proximity correction [OPC] · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title