Cache node processing

Patent metadata

Field	Value
Publication number	US-9317436-B2
Application number	US-201313923370-A
Country	US
Kind code	B2
Filing date	Jun 21, 2013
Priority date	Jun 21, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A technique for cache node processing that includes generating a cache node in response to a request to write data to storage devices. If logical block address (LBA) of the generated cache node is adjacent to LBA of cache nodes of a cache node list, then check if there are cache nodes that are sequential up to a predefined boundary. If there are cache nodes that are sequential up to the predefined boundary, then flush the data of the sequential cache nodes together as a group up to the predefined boundary.

First claim

What is claimed is:

1. A storage controller for cache node processing, comprising:
a cache node list; and
a cache management module to:
generate a cache node in response to a request to write data to storage devices;
in response to a logical block address (LBA) of the cache node that is generated being adjacent to the LBA of cache nodes of the cache node list, check if a total size of cache nodes that are in a consecutively addressed sequential order has reached a predefined boundary, wherein the predefined boundary includes a full stripe of storage configured as a redundant array of independent disk (RAID); and
in response to the total size of the cache nodes that are in the consecutively addressed sequential order having reached the predefined boundary, flush the data of the cache nodes that are sequential together as a group up to the predefined boundary.

2. The storage controller of claim 1 , wherein the cache management module is further configured to determine an insert point to insert the cache node that is generated into the cache node list and then to insert the cache node that is generated into the cache node list at the insert point.

3. The storage controller of claim 1 , wherein the cache management module is further configured to configure the cache nodes of the cache node list to include pointers to memory configured as write cache to hold the data which is to be written to the storage devices.

4. The storage controller of claim 1 , wherein the cache management module is further configured to sort the cache nodes of the cache node list in accordance with an order of the LBA.

5. The storage controller of claim 1 , wherein the cache management module is further configured to:
when an age of the cache node of the cache node list is greater than a time-to-live of the cache node, then flush the data of the cache node to the storage devices.

6. The storage controller of claim 1 , wherein the cache management module is further configured to:
when the LBA of the cache node that is generated and an LBA of previous adjacent cache nodes are sequential, then reset an access time of the cache node that is generated and all previous adjacent cache nodes up to the predefined boundary and indicate that the cache node that is generated and the all previous adjacent cache nodes are sequential cache nodes; and
when the LBA of the cache node that is generated and the LBA of next adjacent cache nodes are sequential, then reset the access time of the cache node that is generated and all next adjacent cache nodes up to the predefined boundary and indicate that the cache node that is generated and the all next adjacent cache nodes are sequential cache nodes.

7. A method for cache node processing, comprising:
generating a cache node in response to a request to write data to storage devices;
in response to a logical block address (LBA) of the cache node that is generated being adjacent to the LBA of cache nodes of a cache node list, checking if a total size of cache nodes that are in a consecutively addressed sequential order has reached a predefined boundary, wherein the predefined boundary includes a full stripe of storage configured as a redundant array of independent disk (RAID); and
in response to the total size of the cache nodes that are in the consecutively addressed sequential order having reached the predefined boundary, flushing the data of the cache nodes that are sequential together as a group up to the predefined boundary.

8. The method of claim 7 , further comprising determining an insert point to insert the cache node that is generated into the cache node list and then inserting the cache node that is generated into the cache node list at the insert point.

9. The method of claim 7 , further comprising configuring the cache nodes of the cache node list to include pointers to memory configured as a write cache to hold the data which is to be written to the storage devices.

10. The method of claim 7 , further comprising sorting the cache nodes of the cache node list in accordance with an order of the LBA.

11. The method of claim 7 , wherein if an age of a cache node of the cache node list is greater than a time-to-live of the cache node, then flushing the data of the cache node to the storage devices.

12. The method of claim 7 , wherein:
when the LBA of the cache node that is generated and LBA of previous adjacent cache nodes are sequential, then resetting an access time of the cache node that is generated and all previous adjacent cache nodes up to the predefined boundary and indicating that the cache node that is generated and the all previous adjacent cache nodes are sequential cache nodes; and
when the LBA of the cache node that is generated and the LBA of next adjacent cache nodes are sequential, then resetting the access time of the cache node that is generated and all next adjacent cache nodes up to the predefined boundary and indicating that the cache node that is generated and the all next adjacent cache nodes are sequential cache nodes.

13. A non-transitory computer-readable medium having computer executable instructions stored thereon for cache node processing, the instructions are executable by a processor to:
generate a cache node in response to a request to write data to storage devices;
in response to a logical block address (LBA) of the cache node that is generated being adjacent to the LBA of cache nodes of a cache node list, check if a total size of cache nodes that are in a consecutively addressed sequential order has reached a predefined boundary, wherein the predefined boundary includes a full stripe of storage configured as a redundant array of independent disk (RAID); and
in response to the total size of the cache nodes that are in the consecutively addressed sequential order having reached the predefined boundary, flush data of the cache nodes that are sequential together as a group up to the predefined boundary.

14. The non-transitory computer-readable medium of claim 13 , further comprising instructions that if executed cause the processor to: determine an insert point to insert the cache node that is generated into the cache node list and then inserting the cache node that is generated into the cache node list at the insert point.

15. The non-transitory computer-readable medium of claim 13 further comprising instructions that if executed cause the processor to: configure the cache nodes of the cache node list to include pointers to memory configured as a write cache to hold the data which is to be written to the storage devices.

16. The non-transitory computer-readable medium of claim 13 further comprising instructions that if executed cause the processor to: sort the cache nodes of the cache node list in accordance with an order of the LBA.

17. The non-transitory computer-readable medium of claim 13 further comprising instructions that if executed cause the processor to:
when an age of a cache node of the cache node list is greater than a time-to-live of the cache node, flush the data of the cache node to the storage devices.

18. The non-transitory computer-readable medium of claim 13 further comprising instructions that if executed cause the processor to:
when the LBA of the cache node that is generated and LBA of previous adjacent cache nodes are sequential, then resetting an access time of the cache node that is generated and all previous adjacent cache nodes up to the predefined boundary and indicating that the cache node that is generated and the all previous adjacent cache nodes are sequential cache nodes;

Assignees

• Hewlett Packard Development Co
• Hewlett Packard Entpr Dev Lp

Inventors

• Pan Weimin

Classifications

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/0871 Primary

  Allocation or management of cache space · CPC title