Machine check summary register

Patent metadata

Field	Value
Publication number	US-9317360-B2
Application number	US-201113995458-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

First claim

What is claimed is:

1. A processor comprising:
a plurality of error reporting registers to each receive error data for a machine check error, wherein the error reporting registers include a control register to control error reporting for machine check errors produced by a particular hardware unit or group of hardware units, an address register to contain the address of the code or data memory location that produced a particular machine check error, a miscellaneous register to contain additional information describing the machine check error to support software recovery of uncorrected errors, a status register to contain information related to a machine check error if its valid flag is set; and
a summary register having settable locations to represent each of the error reporting registers, the settable locations to indicate which of the plurality of the error reporting registers to maintain the error data.

2. The processor as recited in claim 1 , wherein:
the plurality of error reporting registers are arranged in multiple banks, each bank including at least one error reporting register of the plurality of error reporting registers; and
each settable location in the summary register corresponds to one of the banks of the multiple banks.

3. The processor as recited in claim 1 , in which the settable locations in the summary register are to include one or more settable bits to indicate that the error data is maintained in one or more particular error reporting registers.

4. The processor as recited in claim 1 , further comprising logic to set a particular settable location in the summary register in response to receipt of the error data in one or more particular error reporting registers represented by the particular location.

5. The processor as recited in claim 1 , further comprising multiple processor cores, wherein the summary register is a first summary register to represent a first set of the error reporting registers corresponding to a first processor core of the multiple processor cores.

6. The processor as recited in claim 5 , further comprising multiple logical processors corresponding to the first processor core, wherein first summary register and the first set of the error reporting registers correspond to a first logical processor of the multiple logical processors.

7. The processor as recited in claim 6 , further comprising a second summary register to represent a second set of the error reporting registers corresponding to a second logical processor of the multiple logical processors of the first processor core of the multiple processor cores.

8. The processor as recited in claim 1 , further comprising a handler executable by the processor to access the summary register to detect whether one or more of the error reporting registers maintains the error data.

9. The processor as recited in claim 1 , in which the summary register is a first summary register to represent a first type of error data, the processor further comprising a second summary register to represent a second type of error data.

10. A method comprising:
receiving error data in a register of a plurality of registers associated with at least one processor, wherein the plurality of registers include a control register to control error reporting for machine check errors produced by a particular hardware unit or group of hardware units, an address register to contain the address of the code or data memory location that produced a particular machine check error, a miscellaneous register to contain additional information describing the machine check error to support software recovery of uncorrected errors, a status register to contain information related to a machine check error if its valid flag is set;
setting a location in a summary register to indicate a presence of the error data in one of the plurality of registers, the summary register having a plurality of settable locations each corresponding to the plurality of registers;
in response to a notification of an error, accessing the summary register to identify the register of the plurality of registers that received the error data; and
based at least in part on the accessing the summary register, reading the at least one register that received the error data.

11. The method as recited in claim 10 , further comprising, in response to clearing of the error data from the at least one register, resetting the settable location in the summary register to indicate that the error data is not in the register.

12. The method as recited in claim 10 , further comprising at least one of:
storing the error data in an error log; or
initiating recovery from the error.

13. The method as recited in claim 10 , wherein setting the settable location comprises setting a bit at the settable location to indicate the presence of the error data in the at least one register.

14. A system comprising:
at least one processor core;
a plurality of register banks associated with the at least one processor core to receive error data, wherein each of the plurality of register banks includes a control register to control error reporting for machine check errors produced by a particular hardware unit or group of hardware units, an address register to contain the address of the code or data memory location that produced a particular machine check error, a miscellaneous register to contain additional information describing the machine check error to support software recovery of uncorrected errors, a status register to contain information related to a machine check error if its valid flag is set;
a summary register having a plurality of indicators corresponding to the plurality of register banks, a respective indicator of the plurality of indicators to indicate presence of error data in a corresponding register bank; and
a register to provide information about a machine check architecture of the at least one processor core.

15. The system as recited in claim 14 , wherein the summary register is a first summary register of multiple summary registers, the first summary register to correspond to a first processor core of the multiple processor cores.

16. The system as recited in claim 15 , further comprising:
multiple logical processors, including at least a first logical processor and a second logical processor to be provided using the first processor core, the first summary register representing a first plurality of register banks corresponding to the first logical processor; and
a second summary register representing a second plurality of register banks corresponding to the second logical processor.

17. The system as recited in claim 16 , in which there are multiple first summary registers representing the first plurality of register banks corresponding to the first logical processor, and another summary register representing at least the multiple first summary registers.

18. The system as recited in claim 14 , further comprising:
each processor core providing a plurality of logical processors; and
a plurality of the summary registers, at least one summary register corresponding to each logical processor to represent respective register banks corresponding to each logical processor.

Assignees

• Vargas Jose A
• Kumar Mohan J
• Crossland James B
• Nachimuthu Murugasamy K
• Yigzaw Theodros
• Intel Corp

Inventors

• Vargas Jose A
• Kumar Mohan J
• Crossland James B
• Nachimuthu Murugasamy K
• Yigzaw Theodros

Classifications

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title