Interactive scheduling of an application on a multi-core target processor from a co-simulation design environment

Patent metadata

Field	Value
Publication number	US-9317331-B1
Application number	US-201213665635-A
Country	US
Kind code	B1
Filing date	Oct 31, 2012
Priority date	Oct 31, 2012
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

In an embodiment, a method for interactively varying scheduling of a multi-threaded application executing on a symmetric multi-core processor provides an interface in a co-simulation design environment. The interface is associated with a multi-threaded application executing on a target processor that includes symmetric processor cores. The method also sets a scheduling attribute of the multi-threaded application using the interface. The setting occurs when the multi-threaded application is executing. The method further receives data associated with the executing of the multi-threaded application in the co-simulation design environment when the multi-threaded application is executing subsequent to the setting of the scheduling attribute.

First claim

We claim:

1. One or more non-transitory computer-readable media comprising:
one or more instructions that, when executed, cause at least one computing device to:
interact with a co-simulation design environment, the co-simulation design environment for co-simulating a model such that a first component of the model is executed on a host device as part of the co-simulating and a second component of the model is executed on a target processor having a plurality of processor cores as part of the co-simulating;
use an interface to communicate with the target processor;
allocate execution of the second component to two or more of the plurality of processor cores of the target processor using the interface;
receive an interactive instruction from the co-simulation design environment on the host device, the interactive instruction to alter allocation of at least a portion of the execution of the second component;
receive execution data regarding the second component executing on the two or more of the plurality of processor cores of the target processor, the receiving occurring in the co-simulation design environment via the interface; and
alter, via the interface, allocation of the at least a portion of the execution of the second component based on the received execution data on the two or more of the plurality of processor cores, the allocating and altering occurring without re-generating, re-compiling or re-running code for the model.

2. The medium of claim 1 , wherein the allocating and altering occur when the second component is executing on the plurality of processor cores of the target processor.

3. The one or more non-transitory computer-readable media of claim 1 , wherein the altering is performed based on one or more of an input received from a person, a program and an algorithm.

4. The medium of claim 1 , further comprising:
one or more instructions that, when executed, cause the at least one computing device to:
receive execution data regarding the second component executing on the one or more of the plurality processor cores of the target processor, the receiving occurring:
in the co-simulation design environment via the interface, and
when the second component is executing.

5. The one or more non-transitory computer-readable media of claim 1 , wherein the altering is based on the received execution data.

6. The one or more non-transitory computer-readable media of claim 1 , further comprising:
one or more instructions that, when executed, cause the at least one computing device to:
display the received data in the co-simulation design environment during the executing of the second component on the target processor; and
receive subsequent data in the co-simulation design environment during the executing, the subsequent data associated with the executing of the second component following the altering allocation of the at least a portion of the execution of the second component.

7. The one or more non-transitory computer-readable media of claim 1 , wherein the received data associated with the executing of the second component includes statistical data relating to the executing of the second component on the target processor.

8. The one or more non-transitory computer-readable media of claim 7 , wherein the statistical data includes data relating to at least one of:
a buffer allocation, algorithm data synchronization information, or an inter-thread wait time and CPU utilization by the plurality of processor cores.

9. The one or more non-transitory computer-readable media of claim 1 , further comprising:
one or more instructions that, when executed, cause the at least one computing device to:
log the received data.

10. The one or more non-transitory computer-readable media of claim 1 , further comprising:
one or more instructions that, when executed, cause the at least one computing device to:
generate a fixed mapping between the execution of the second component and the plurality of processor cores of the target processor.

11. The one or more non-transitory computer-readable media of claim 10 , wherein the fixed mapping is an optimal fixed mapping.

12. The one or more non-transitory computer-readable media of claim 1 , further comprising:
one or more instructions that, when executed, cause the at least one computing device to:
generate a conventional dynamic scheduler.

13. The one or more non-transitory computer-readable media of claim 12 , wherein the conventional dynamic scheduler implements a rule set, the rule set used in allocating the execution of the second component to the plurality of processor cores of the target processor.

14. The one or more non-transitory computer-readable media of claim 1 , wherein the allocating is based on a plurality of rule sets, the plurality of rule sets being organized in a hierarchy.

15. The one or more non-transitory computer-readable media of claim 14 , comprising:
one or more instructions that, when executed, cause the at least one computing device to:
generate an optimal conventional dynamic scheduler.

16. The one or more non-transitory computer-readable media of claim 15 , wherein:
the plurality of rule sets includes an optimal rule set, and
the optimal conventional dynamic scheduler implements the optimal rule set.

17. The one or more non-transitory computer-readable media of claim 1 , wherein the allocation identifies processor core affinity.

18. The one or more non-transitory computer-readable media of claim 1 , wherein the allocation identifies thread priority.

19. The one or more non-transitory computer-readable media of claim 1 , wherein the allocation maintains data synchronization within the model.

20. The one or more non-transitory computer-readable media of claim 1 , wherein the model is a graphical model that includes a plurality of blocks and subsystems, the one or more non-transitory computer-readable media comprising:
one or more instructions that, when executed, cause the at least one computing device to:
allocate execution of respective ones of the plurality of blocks and subsystems to separate cores in the plurality of processor cores.

21. A method for interactively varying scheduling of a multi-threaded application, the method comprising:
interacting with a co-simulation design environment, the co-simulation design environment for co-simulating a model such that a first component of the model is executed on a host device as part of the co-simulating and a second component of the model is executed on a target processor having a plurality of processor cores as part of the co-simulating;
using an interface to communicate with the target processor;
allocating execution of the second component to two or more of the plurality of processor cores of the target processor using the interface;
receiving an interactive instruction from the co-simulation design environment on the host device, the interactive instruction to alter allocation of at least a portion of the execution of the second component;
receiving execution data regarding the second component executing on the one or more of the plurality of processor cores of the target processor, the receiving occurring in the co-simulation design environment via the interface; and
altering, via the interface, allocation of the at least a portion of the execution of the second component based on the received execution data on the two or more of the plurality of processor cores, the allocating and altering occurring without re-generating, re-compil

Assignees

• Mathworks Inc

Inventors

• Koh David
• Belge Murat

Classifications

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/5066 Primary

  Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451) · CPC title