Microprocessor with boot indicator that indicates a boot ISA of the microprocessor as either the X86 ISA or the ARM ISA

Patent metadata

Field	Value
Publication number	US-9317301-B2
Application number	US-201414526029-A
Country	US
Kind code	B2
Filing date	Oct 28, 2014
Priority date	Apr 7, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.

First claim

We claim:

1. A microprocessor, comprising:
a plurality of registers, that holds an architectural state of the microprocessor;
an indicator, that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA;
a hardware instruction translator, that translates x86 ISA instructions and ARM ISA instructions into microinstructions, wherein the hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal;
an execution pipeline, coupled to the hardware instruction translator, wherein the execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions; and
wherein in response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.

2. The microprocessor of claim 1 , wherein the indicator comprises a default value in microcode of the microprocessor.

3. The microprocessor of claim 2 , further comprising:
a fuse, which may be blown to invert the default value in the microcode.

4. The microprocessor of claim 2 , wherein the default value in the microcode is modifiable by a microcode patch applied prior to the microprocessor fetching its initial ISA instruction from architectural memory space after being reset.

5. The microprocessor of claim 1 , wherein the indicator comprises a bit in a register of the microprocessor that has a default value in response to the reset signal.

6. The microprocessor of claim 1 , wherein the indicator comprises an external input to the microprocessor.

7. The microprocessor of claim 1 , wherein in response to the reset signal the microprocessor fetches the initial ISA instructions from architectural memory space at an address defined by the boot ISA.

8. A method, comprising:
detecting that a reset of a microprocessor has been signaled, wherein said detecting is performed by the microprocessor;
determining, in response to said detecting that a reset of the microprocessor has been signaled, which of the x86 instruction set architecture (ISA) and the Advanced RISC Machines (ARM) ISA an indicator of the microprocessor indicates is a boot ISA of the microprocessor, wherein said determining is performed by the microprocessor;
initializing an architectural state of the microprocessor as defined by the boot ISA, wherein said initializing is performed by the microprocessor;
translating into microinstructions the initial ISA instructions fetched from architectural memory space by the microprocessor after the reset as instructions of the boot ISA, wherein said translating is performed by a hardware instruction translator of the microprocessor; and
executing the microinstructions to generate results defined by the boot ISA, wherein said executing is performed by an execution pipeline of the microprocessor coupled to the hardware instruction translator.

9. The method of claim 8 , wherein the indicator comprises a default value in microcode of the microprocessor.

10. The method of claim 9 , further comprising:
inverting the default value in the microcode in response to sensing a blown fuse of the microprocessor.

11. The method of claim 9 , wherein the default value in the microcode is modifiable by a microcode patch applied prior to the microprocessor fetching its initial ISA instruction from architectural memory space after being reset.

12. The method of claim 8 , wherein the indicator comprises a bit in a register of the microprocessor that has a default value in response to the reset signal.

13. The method of claim 8 , wherein the indicator comprises an external input to the microprocessor.

14. The method of claim 8 , further comprising:
fetching the initial ISA instructions after the reset at an address defined by the boot ISA.

15. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:
computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising:
first program code for specifying a plurality of registers, that holds an architectural state of the microprocessor;
second program code for specifying an indicator, that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA;
third program code for specifying a hardware instruction translator, that translates x86 ISA instructions and ARM ISA instructions into microinstructions, wherein the hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal;
fourth program code for specifying an execution pipeline, coupled to the hardware instruction translator, wherein the execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions; and
wherein in response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.

16. The computer program product of claim 15 , wherein the indicator comprises a default value in microcode of the microprocessor.

17. The computer program product of claim 16 , further comprising:
a fuse, which may be blown to invert the default value in the microcode.

18. The computer program product of claim 15 , wherein the indicator comprises a bit in a register of the microprocessor that has a default value in response to the reset signal.

19. The computer program product of claim 15 , wherein the indicator comprises an external input to the microprocessor.

20. The computer program product of claim 15 , wherein in response to the reset signal the microprocessor fetches the initial ISA instructions from architectural memory space at an address defined by the boot ISA.

Assignees

• Via Tech Inc

Inventors

• Henry G Glenn
• Parks Terry
• Hooker Rodney E

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30076 Primary

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F9/3017

  Runtime instruction translation, e.g. macros · CPC title

• G06F9/30123

  according to context, e.g. thread buffers · CPC title