Apparatus and method for implementing instruction support for the camellia cipher algorithm

Patent metadata

Field	Value
Publication number	US-9317286-B2
Application number	US-41483109-A
Country	US
Kind code	B2
Filing date	Mar 31, 2009
Priority date	Mar 31, 2009
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.

First claim

What is claimed is:

1. A processor, comprising:
an instruction fetch unit configured to issue instructions for execution, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA);
an execution unit configured to execute at least some of the instructions defined within the ISA; and
a cryptographic unit configured to receive particular instructions for execution from the instruction fetch unit, wherein the cryptographic unit includes a plurality of sub-units, wherein the particular instructions include one or more Camellia instructions defined within said ISA, wherein each of the one or more Camellia instructions includes opcode bits specifying a particular Camellia operation and is executable by a corresponding sub-unit of the plurality of sub-units to implement a portion of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713), wherein the portion of the Camellia cipher that is implemented responsive to execution of a given Camellia instruction is dependent upon an opcode encoded in the opcode bits of the given Camellia instruction;
wherein in response to executing a Camellia F( )-operation instruction of the one or more Camellia instructions, a given sub-unit of the plurality of sub-units is configured to perform a sequence of operations upon a data input operand and a subkey operand, wherein the sequence of operations includes a plurality of Boolean operations, a plurality of shift operations, and a plurality of substitution operations as defined by the Camellia cipher, wherein the data input operand is dependent upon a previous execution of a given Camellia operation, and wherein the subkey operand corresponds to a given one of a plurality of subkeys generated by expanding an initial key.

2. The processor as recited in claim 1 , wherein in response to executing the Camellia F( )-operation instruction, the cryptographic unit is further configured to combine a result of a previous iteration of the F( ) operation with a third operand specified by the Camellia F( )-operation instruction using an exclusive-OR (XOR) operation, and to output a result of the XOR operation as a result of the Camellia F( )-operation instruction.

3. The processor as recited in claim 1 , wherein in response to executing a Camellia FL( )-operation instruction of the one or more Camellia instructions, the cryptographic unit is further configured to perform upon a data input operand and a subkey operand, a second plurality of Boolean operations as defined by the Camellia cipher.

4. The processor as recited in claim 1 , wherein in response to executing a Camellia FLI( ) operation instruction of the one or more Camellia instructions, the cryptographic unit is further configured to perform upon a data input operand and a subkey operand, a third plurality of Boolean operations as defined by the Camellia cipher.

5. The processor as recited in claim 1 , wherein during each one of a plurality of consecutive execution cycles, the cryptographic unit is further configured to receive a newly-issued one of the one or more Camellia instructions for execution.

6. The processor as recited in claim 1 , wherein for at least two consecutive execution cycles, the ones of the one or more Camellia instructions issued for execution during the at least two consecutive execution cycles are assigned to different ones of a plurality of threads.

7. The processor as recited in claim 1 , wherein the ISA is compliant with a version of the SPARC ISA.

8. A system, comprising:
a system memory, and
the processor as recited in claim 1 coupled to the system memory.

9. A method, comprising:
a hardware processor issuing instructions for execution by an execution unit within the hardware processor, wherein the instructions are programmer-selectable from a defined instruction set architecture (ISA);
a hardware cryptographic unit of the processor receiving particular instructions for execution, wherein the hardware cryptographic unit includes a plurality of sub-units, wherein the particular instructions include one or more Camellia instructions defined within said ISA, wherein each of the one or more Camellia instructions includes opcode bits specifying a particular Camellia operation and is executable by the cryptographic unit a corresponding sub-unit of the plurality of sub-units to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713, wherein the portion of the Camellia cipher that is implemented responsive to execution of a given Camellia instruction is dependent upon an opcode encoded in the opcode bits of the given Camellia instruction; and
wherein in response to executing a Camellia F( )-operation instruction of the one or more Camellia instructions, a given sub-unit of the plurality of sub-units is configured to perform a sequence of operations upon a data input operand and a subkey operand, wherein the sequence of operations includes a plurality of Boolean operations, a plurality of shift operations, and a plurality of substitution operations as defined by the Camellia cipher, wherein the data input operand is dependent upon a previous execution of a given Camellia operation, and wherein the subkey operand corresponds to a given one of a plurality of subkeys generated by expanding an initial key.

10. The method as recited in claim 9 , further comprising:
in response to executing the Camellia F( )-operation instruction, the hardware cryptographic unit combining a result of a previous iteration of the F( ) operation with a third operand specified by the Camellia F( )-operation instruction using an exclusive-OR (XOR) operation, and outputting a result of the XOR operation as a result of the Camellia F( )-operation instruction.

11. The method as recited in claim 10 , further comprising:
during processing of a given round of the Camellia cipher, specifying result data from a prior round of the Camellia cipher as the third operand of the Camellia F( )-operation instruction.

12. The method as recited in claim 9 , further comprising:
in response to executing a Camellia FL( )-operation instruction of the one or more Camellia instructions, the hardware cryptographic unit performing upon a data input operand and a subkey operand, a second plurality of Boolean operations as defined by the Camellia cipher.

13. The method as recited in claim 9 , further comprising:
in response to executing a Camellia FLI( )-operation instruction of the one or more Camellia instructions, the hardware cryptographic unit performing upon a data input operand and a subkey operand, a third plurality of Boolean operations as defined by the Camellia cipher.

14. The method as recited in claim 9 , further comprising:
during each one of a plurality of consecutive execution cycles, the hardware cryptographic unit receiving a newly-issued one of the one or more Camellia instructions for execution.

15. The method as recited in claim 14 , wherein for at least two consecutive execution cycles, the ones of the one or more Camellia instructions issued for execution during the at least two consecutive execution cycles are assigned to different ones of a plurality of threads.

16. The method as recited in claim 9 , wherein the ISA is compliant with a version of the SPARC ISA.

Assignees

• Olson Christopher H
• Grohoski Gregory F
• Spracklen Lawrence A
• Oracle America Inc

Inventors

• Olson Christopher H
• Grohoski Gregory F
• Spracklen Lawrence A

Classifications

• H04L2209/24

  Key scheduling, i.e. generating round keys or sub-keys for block encryption · CPC title

• H04L2209/122

  Hardware reduction or efficient architectures · CPC title

• G06F9/30018

  Bit or string instructions · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• H04L9/0625

  with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI · CPC title