Vector hazard check instruction with reduced source operands

Patent metadata

Field	Value
Publication number	US-9317284-B2
Application number	US-201314034658-A
Country	US
Kind code	B2
Filing date	Sep 24, 2013
Priority date	Sep 24, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

In an embodiment, a processor may implement a vector hazard check instruction to detect dependencies between vector memory operations based on the addresses of the vectors accessed by the vector memory operations. The addresses may be specified via a base address and a vector of indexes for each vector. In an embodiment, one of the base addresses may be an implied (or assumed) zero address, reducing the number of operands of the hazard check instruction.

First claim

What is claimed is:

1. A processor comprising an execution core configured to execute an instruction having source operands that include a first scalar value and one or more vectors of indexes corresponding to a first vector memory operation and a second vector memory operation, wherein the execution core is configured to detect whether or not a dependency exists between the first vector memory operation and the second memory operation, wherein the detection of whether or not a dependency exists is based on the first scalar value and the one or more vectors of indexes, and wherein the execution core is configured to generate a dependency vector that indicates, for each first element of a first vector accessed by the first vector memory operation that depends on a second element of a second vector accessed by the second memory operation, which second element that the first element depends on.

2. The processor as recited in claim 1 wherein the processor is configured to detect the dependency between a first vector of addresses and a second vector of addresses, wherein the first vector of addresses are based on a first vector of indexes from the one or more vectors of indexes added to an implied base address of zero.

3. The processor as recited in claim 2 wherein the second vector of addresses are based on the first vector of indexes added to the first scalar value.

4. The processor as recited in claim 2 wherein the second vector of addresses are based on a second vector of indexes from the one or more vectors of indexes added to the first scalar value.

5. The processor as recited in claim 1 wherein the processor is configured to detect the dependency between a first vector of addresses and a second vector of addresses, wherein the first vector of addresses are based on a first vector of indexes from the one or more vectors of indexes.

6. The processor as recited in claim 1 wherein the one or more vectors of indexes are scaled by a first data size of the first vector memory operation for addresses of the first vector.

7. The processor as recited in claim 6 wherein the one or more vectors of indexes are scaled by a second data size of the first vector memory operation for addresses of the second vector.

8. The processor as recited in claim 1 wherein the source operands of the instruction further include a first predicate, the first predicate indicating which elements of the second vector are active, and wherein the execution core is configured to generate the dependency vector responsive to the first predicate.

9. The processor as recited in claim 8 wherein the source operands of the instruction further include a second predicate, the second predicate indicating which elements of the first vector are active, and wherein the execution core is configured to generate the dependency vector responsive to the second predicate.

10. A method comprising:
a processor executing a first instruction to compute a difference between a first base address of a first vector and a second base address of a second vector; and
the processor executing a second instruction having source operands that include the difference and one or more vectors of indexes corresponding to a first vector memory operation that accesses the first vector and a second vector memory operation that accesses the second vector, wherein executing the second instruction includes:
detecting whether or not a dependency exists between the first vector memory operation and the second memory operation based on the difference and the one or more vectors of indexes; and
generating a dependency vector that indicates, for each first element of the first vector that depends on a second element of the second vector, which second element that the first element depends on.

11. The method as recited in claim 10 wherein detecting whether or not the dependency exists is between a first vector of addresses and a second vector of addresses, wherein the first vector of addresses are based on a first vector of indexes from the one or more vectors of indexes.

12. The method as recited in claim 11 wherein the second vector of addresses are based on the first vector of indexes added to the difference.

13. The method as recited in claim 11 wherein the second vector of addresses are based on a second vector of indexes from the one or more vectors of indexes added to the difference.

14. The method as recited in claim 10 wherein the one or more vectors of indexes are scaled by a first data size of the first vector memory operation for addresses of the first vector and the one or more vectors of indexes are scaled by a second data size of the second vector memory operation for addresses of the second vector.

15. The method as recited in claim 10 wherein the instruction further includes a first predicate and a second predicate as source operands, the first predicate indicating which elements of the first vector are active, and the second predicate indication which elements of the second vector are active, and wherein generating the dependency vector is further responsive to the first predicate and the second predicate.

16. A processor comprising an execution core configured to execute an instruction having source operands that include one or more vectors of indexes corresponding to a first vector memory operation and a second vector memory operation and at least one vector attribute corresponding to a first vector accessed by the first vector memory operation, wherein the execution core is configured to detect whether or not a dependency exists between the first vector memory operation and the second memory operation, wherein the detection of whether or not a dependency exists is based on the vector attribute and the one or more vectors of indexes, and wherein the execution core is configured to generate a dependency vector that indicates, for each first element of a first vector accessed by the first vector memory operation that depends on a second element of a second vector accessed by the second memory operation, which second element that the first element depends on.

17. The processor as recited in claim 16 wherein the source operands of the instruction further include a second vector attribute of the second vector, and wherein the detection of whether or not the dependency exists is further based on the second vector attribute.

18. The processor as recited in claim 17 wherein a first vector of indexes of the one or more vectors of indexes are scaled by the first vector attribute for a first vector of addresses corresponding to the first vector and wherein a second vector of indexes of the one or more vectors of indexes are scaled by the second vector attribute for a second vector of addresses corresponding to the second vector.

19. The processor as recited in claim 17 wherein a first vector of indexes of the one or more vectors of indexes are scaled by the first vector attribute for a first vector of addresses corresponding to the first vector and wherein the first vector of indexes of the one or more vectors of indexes are scaled by the second vector attributes for a second vector of addresses corresponding to the second vector.

20. The processor as recited in claim 16 further comprising one or more predicates included as source operands of the instruction, wherein the generation of the dependency vector is further based on the one or more predicates.

Assignees

• Apple Inc

Inventors

• Gonion Jeffry E
• Klaiber Alexander C

Classifications

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/30038

  using a mask · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title