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Low complexity gate line driver circuitry
US9317151B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9317151-B2 |
| Application number | US-201313747872-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 23, 2013 |
| Priority date | May 14, 2012 |
| Publication date | Apr 19, 2016 |
| Grant date | Apr 19, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
Gate driver circuitry that controls an array of display elements is described. The gate driver circuitry has gate drivers that apply a control pulse to each of a number of gate lines in sequence, from a previous gate line to a current gate line, during a frame interval in which the array of display elements is filled with pixel values. Each gate driver has a latch stage followed by an output stage. The output stage is coupled to drive a current gate line, and the latch stage is coupled to drive a) a first hold circuit that holds the current gate line at a predetermined voltage, and b) a second hold circuit that holds a previous gate line at a predetermined voltage. Other embodiments are also described and claimed.
First claim
Opening claim text (preview).
What is claimed is: 1. An electronic device comprising: a plurality of gate lines; and a plurality of gate drivers each having a latch stage followed by an output stage, the output stage being coupled to drive a current gate line, and wherein the gate driver is coupled to drive a) a first hold circuit that holds the current gate line at a predetermined voltage, and b) a second hold circuit that holds a previous gate line at a predetermined voltage, and wherein each gate driver f…
Assignees
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Classifications
Physics · mapped topic
- G06F3/0412Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9317151B2 cover?
- Gate driver circuitry that controls an array of display elements is described. The gate driver circuitry has gate drivers that apply a control pulse to each of a number of gate lines in sequence, from a previous gate line to a current gate line, during a frame interval in which the array of display elements is filled with pixel values. Each gate driver has a latch stage followed by an output st…
- Who is the assignee on this patent?
- Apple Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F3/0412. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).