Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9316789-B2
Application number	US-201514796523-A
Country	US
Kind code	B2
Filing date	Jul 10, 2015
Priority date	Jan 2, 2012
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A semiconductor device includes a single crystalline substrate, an electrical element and an optical element. The electrical element is disposed on the single crystalline substrate. The electrical element includes a gate electrode extending in a crystal orientation <110> and source and drain regions adjacent to the gate electrode. The source region and the drain region are arranged in a direction substantially perpendicular to a direction in which the gate electrode extends. The optical element is disposed on the single crystalline substrate. The optical element includes an optical waveguide extending in a crystal orientation <010>.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming an optical element on a single crystalline substrate, the optical element comprising an optical waveguide extending in a crystal orientation <010>; and
forming an electrical element comprising a gate electrode extending in a crystal orientation <110>, and source and drain regions adjacent to the gate electrode, the source and drain regions arranged in a direction substantially perpendicular to a direction in which the gate electrode extends,
coupling an input grating coupler to a first interferometer which is coupled to a first end of the optical waveguide, and
coupling an output grating coupler to a second interferometer which is coupled to a second end of the optical waveguide, a linear direction between the input grating coupler and the output grating coupler being substantially 45° oblique from a linear direction between the source region and the drain region.

2. A method of manufacturing a semiconductor device, comprising:
forming an optical element on a single crystalline substrate, the optical element comprising an optical waveguide extending in a crystal orientation <010>; and
forming an electrical element comprising a gate electrode extending in a crystal orientation <110>, and source and drain regions adjacent to the gate electrode, the source and drain regions arranged in a direction substantially perpendicular to a direction in which the gate electrode extends,
wherein forming the optical element comprises:
forming a first cladding layer on the single crystalline substrate;
forming an amorphous layer on the first cladding layer and the single crystalline substrate;
crystallizing the amorphous layer to form an epitaxial layer having a crystal orientation substantially the same as that of the single crystalline substrate;
partially removing the epitaxial layer to form a core layer extending in a crystal orientation <010>; and
forming a second cladding layer on the first cladding layer to cover the core layer.

3. The method of claim 2 , further comprising prior to forming the first cladding layer, partially removing the single crystalline substrate to form a trench extending the crystal orientation <010>, wherein the first cladding layer partially fills the trench.

4. The method of claim 2 , wherein the first and second cladding layers comprise silicon oxide, silicon nitride or silicon carbon nitride.

5. The method of claim 1 ,
wherein forming the optical element further comprises forming a phase converter, and
wherein the phase converter is optically connected with the optical waveguide.

6. A method of manufacturing a semiconductor device, comprising:
forming an optical element on a single crystalline substrate, the optical element comprising an optical waveguide extending in a crystal orientation <010>; and
forming an electrical element comprising a gate electrode extending in a crystal orientation <110>, and source and drain regions adjacent to the gate electrode, the source and drain regions arranged in a direction substantially perpendicular to a direction in which the gate electrode extends,
wherein forming the electrical element comprises:
forming a buried insulation layer on the single crystalline substrate;
forming an amorphous layer on the buried insulation layer;
crystallizing the amorphous layer to form an epitaxial layer having a crystal orientation substantially the same as that of the single crystalline substrate;
forming the gate electrode on the epitaxial layer; and
forming the source region and the drain region adjacent to the gate electrode, the source region and the drain region being at upper portions of the epitaxial layer.

7. The method of claim 1 , wherein the electrical element comprises a dynamic random access memory (DRAM) device, a flash memory device, a phase-change random access memory (PRAM) device, a magnetic random access memory (MRAM) device, or a resistive random access memory (RRAM) device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ki Chul
• Kuh Bong Jin
• Won Jung Yun
• Lee Eun Ha
• Choi Han Mei

Classifications

• H10D30/021

  of FETs having insulated gates [IGFET] · CPC title

• H10F99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• G02B2006/121

  Channel; buried or the like · CPC title

• G02B6/122

  Basic optical elements, e.g. light-guiding paths · CPC title

• G02B6/13 Primary

  Integrated optical circuits characterised by the manufacturing method · CPC title