Substrate structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9313886-B2
Application number	US-201414447575-A
Country	US
Kind code	B2
Filing date	Jul 30, 2014
Priority date	Apr 28, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A manufacturing method of a substrate structure includes the following steps. A substrate including a supporting layer, two release layers and two base metal layers is provided. The release layers are disposed on two opposite surfaces of the supporting layer respectively. Each base metal layer covers each of the release layers. A first patterned solder-resist layer is formed on each of the base metal layers. A stacking layer is laminated on each of the base metal layers to cover each of the first patterned solder-resist layers. Each stacking layer includes a dielectric layer and a metal foil. Each dielectric layer is disposed between the corresponding base metal layer and the corresponding metal foil. Each base metal layer is separated from the supporting layer. Each base metal layer is patterned to form a patterned metal layer on each stacking layer. Each patterned metal layer exposes the corresponding first patterned solder-resist layer.

First claim

What is claimed is:

1. A manufacturing method of a substrate structure, comprising:
providing a substrate, the substrate comprising a supporting layer, two release layers and two base metal layers, the two release layers disposed on two opposite surfaces of the supporting layer respectively, the two base metal layers covering the two release layers respectively;
forming two etch stop layers on each of the base metal layers;
forming two patterned metal layers on each of the etch stop layers, each of the patterned metal layers comprising a plurality of openings to expose a corresponding portion of the etch stop layer, wherein each of the etch stop layers is located between each of the base metal layers and each of the patterned metal layers;
forming two first patterned solder-resist layers on each of the patterned metal layers to cover the exposed portion of the base metal layer;
laminating a stacking layer on each of the patterned metal layers, each of the stacking layers covering the corresponding first patterned solder-resist layer, wherein each of the stacking layers comprises a dielectric layer and a metal foil, and each of the dielectric layers is disposed between the corresponding patterned metal layer and the corresponding metal foil;
separating each of the base metal layers from the release layer to remove the supporting layer;
removing each of the base metal layers by etching to expose each of the etch stop layers; and
removing each of the etch stop layers to expose each of the patterned metal layers and each of the first patterned solder-resist layers.

2. The manufacturing method of a substrate structure as claimed in claim 1 , wherein each of the etch stop layers comprises a nickel layer.

3. The manufacturing method of a substrate structure as claimed in claim 1 , wherein a method of forming the patterned metal layer on each of the base metal layers comprises an additive process.

4. The manufacturing method of a substrate structure as claimed in claim 1 , further comprising:
forming a second patterned solder-resist layer on each of the first patterned solder-resist layers and each of the metal foils, each of the second patterned solder-resist layers partially covering the corresponding the patterned metal layers; and
forming a surface finish layer on each of the patterned metal layers to cover the exposed portion of the patterned metal layer.

5. The manufacturing method of a substrate structure as claimed in claim 1 , further comprising:
forming a surface finish layer on each of the patterned metal layers and each of the metal foils.

6. The manufacturing method of a substrate structure as claimed in claim 5 , wherein each of the surface finish layers comprises an organic solderability preservatives (OSP) layer, an electroless nickel and immersion gold (ENIG) layer, an immersion silver (I-Ag) layer, an immersion tin (I-Sn) layer, an immersion bismuth (I-Bi) layer, a hot air solder leveling (HASL) layer, a nickel and gold electroplating layer, an electroless Pd/Ni layer, an electroless Pd/Cu layer, or a Sn—Bi alloy electroplating layer.

7. The manufacturing method of a substrate structure as claimed in claim 1 , wherein each of the release layers comprises a fluorine release film, a polyethylene (PE) release film, or a polyethylene terephthalate (PET) release film.

Assignees

• Wang chao-min
• Subtron Technology Co Ltd

Inventors

• Wang chao-min

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W70/66

  Conductive materials thereof · CPC title