DC coefficient signaling at small quantization step sizes

Patent metadata

Field	Value
Publication number	US-9313509-B2
Application number	US-81502910-A
Country	US
Kind code	B2
Filing date	Jun 14, 2010
Priority date	Jul 18, 2003
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Described tools and techniques relate to signaling for DC coefficients at small quantization step sizes. The techniques and tools can be used in combination or independently. For example, a tool such as a video encoder or decoder processes a VLC that indicates a DC differential for a DC coefficient, a FLC that indicates a value refinement for the DC differential, and a third code that indicates the sign for the DC differential. Even with the small quantization step sizes, the tool uses a VLC table with DC differentials for DC coefficients above the small quantization step sizes. The FLCs for DC differentials have lengths that vary depending on quantization step size.

First claim

We claim:

1. A method of coding/decoding video, the method comprising, with a computing device that implements a video encoder and/or video decoder:
determining a quantization step size, wherein one or more syntax elements in a bit stream indicate the quantization step size;
processing a variable length code (VLC) for a DC differential for a DC coefficient using a VLC table that includes different VLC values associated with different values for the DC differential, wherein the VLC table further includes an escape code that indicates presence of a fixed length code (FLC) for the DC differential for the DC coefficient; and
when the VLC is the escape code:
using the quantization step size to determine a length of the FLC for the DC differential for the DC coefficient, wherein the length of the FLC varies depending on the quantization step size; and
processing the FLC for the DC differential for the DC coefficient.

2. The method of claim 1 further comprising, with the computing device, reconstructing the DC coefficient during decoding based at least in part on the FLC.

3. The method of claim 1 wherein the FLC indicates a value for the DC differential.

4. The method of claim 1 further comprising, during decoding, with the computing device:
computing a DC predictor;
reconstructing the DC differential based at least in part on the escape code and the FLC; and
combining the DC predictor and the DC differential.

5. The method of claim 1 further comprising, during encoding, with the computing device:
computing a DC predictor;
computing the DC differential based at least in part on the DC predictor and the DC coefficient; and
representing the DC differential with the escape code and the FLC.

6. The method of claim 1 wherein:
if the quantization step size is 1, the length of the FLC is 10;
if the quantization step size is 2, the length of the FLC is 9; and
otherwise, the quantization step size being greater than 2, the length of the FLC is 8.

7. A computer-implemented method of decoding video using a computing device that implements a video decoder, the method comprising, with the computing device that implements the video decoder:
determining a quantization step size for a block of a video picture based on one or more syntax elements in a bit stream;
receiving a variable length code (VLC) in the bit stream, wherein the VLC at least in part indicates a DC differential for a DC coefficient of the block of the video picture;
determining that the VLC indicates an escape code in a VLC table, the escape code indicating presence in the bit stream of a fixed length code (FLC) for the DC differential, the VLC table also including different VLC values associated with different values for DC differentials;
using the quantization step size to determine a length of the FLC for the DC differential in the bit stream, wherein the length of the FLC varies depending on the quantization step size;
receiving the FLC in the bit stream; and
decoding the FLC to determine a value for the DC differential; and
reconstructing the DC coefficient using the value for the DC differential, wherein the DC differential represents a difference between the DC coefficient and a DC predictor.

8. The method of claim 7 wherein:
if the quantization step size is 1, the length of the FLC is 10;
if the quantization step size is 2, the length of the FLC is 9; and
otherwise, the quantization step size being greater than 2, the length of the FLC is 8.

9. The method of claim 7 wherein the quantization step size is indicated at least in part by a picture-layer syntax element for the video picture and at least in part by a differential quantization syntax element that adjusts the quantization step size for a macroblock that includes the block.

10. The method of claim 7 wherein the VLC table is selected from among multiple sets of VLC tables.

11. The method of claim 10 wherein each of the multiple sets of VLC tables includes a table for DC differentials for luminance blocks and a table for DC differentials for chrominance blocks, wherein a first set of the multiple sets of VLC tables is adapted for low motion video, and wherein a second set of the multiple sets of VLC tables is adapted for high motion video.

12. The method of claim 7 further comprising, with the computing device that implements the video decoder, receiving a code in the bit stream that represents a sign value for the DC differential.

13. The method of claim 7 further comprising, for another block of the video picture:
determining a quantization step size for the other block of the video picture;
receiving another VLC in the bit stream, wherein the other VLC at least in part indicates a DC differential for a DC coefficient of the other block of the video picture;
determining that the other VLC does not indicate the escape code in the VLC table;
determining a base value for the DC differential for the DC coefficient of the other block using the other VLC;
receiving a code in the bit stream that indicates a refinement value;
multiplying the base value by a factor that varies depending on the quantization step size for the other block of the video picture; and
adding the refinement value to a result of the multiplying.

14. A computing device comprising a processor and memory, wherein the computing device implements a video decoder configured to perform operations comprising:
determining a quantization step size for a block of a video picture based on one or more syntax elements in a bit stream;
receiving a variable length code (VLC) in the bit stream, wherein the VLC at least in part indicates a DC differential for a DC coefficient of the block of the video picture;
determining that the VLC indicates an escape code in a VLC table, the escape code indicating presence in the bit stream of a fixed length code (FLC) for the DC differential, the VLC table also including different VLC values associated with different values for DC differentials;
using the quantization step size to determine a length of the FLC for the DC differential in the bit stream, wherein the length of the FLC varies depending on the quantization step size;
receiving the FLC in the bit stream;
decoding the FLC to determine a value for the DC differential; and
reconstructing the DC coefficient using the value for the DC differential, wherein the DC differential represents a difference between the DC coefficient and a DC predictor.

15. The computing device of claim 14 wherein:
if the quantization step size is 1, the length of the FLC is 10;
if the quantization step size is 2, the length of the FLC is 9; and
otherwise, the quantization step size being greater than 2, the length of the FLC is 8.

16. The computing device of claim 14 wherein the quantization step size is indicated at least in part by a picture-layer syntax element for the video picture and at least in part by a differential quantization syntax element that adjusts the quantization step size for a macroblock that includes the block.

17. The computing device of claim 14 wherein the VLC table is selected from among multiple sets of VLC tables.

18. The computing device of claim 17 wherein each of the multiple sets of VLC tables includes a table for DC differentials for luminance blocks and a table for DC differentials for chrominance blocks, wherein a first set of the multiple sets of VLC tables is adapted for low motion video, and wherein a second set of the multiple sets of VLC tables is adapted for high motion video.

19. The computing

Assignees

• Lin Chih-Lung
• Regunathan Shankar
• Srinivasan Sridhar
• Microsoft Technology Licensing Llc

Inventors

• Lin Chih-Lung
• Regunathan Shankar
• Srinivasan Sridhar

Classifications

• H04N19/46

  Embedding additional information in the video signal during the compression process (H04N19/517, H04N19/68, H04N19/70 take precedence) · CPC title

• H04N19/18 Primary

  the unit being a set of transform coefficients · CPC title

• H04N19/136

  Incoming video signal characteristics or properties · CPC title

• H04N19/61

  in combination with predictive coding · CPC title

• H04N19/184

  the unit being bits, e.g. of the compressed video stream · CPC title