Imaging sensors

Patent metadata

Field	Value
Publication number	US-9313428-B2
Application number	US-201414574383-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	Dec 26, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Described herein is a pixel readout circuit which provides readout at two sensitivity levels depending on the amount of electrons generated by a pixel photodiode in the circuit. A floating diffusion capacitor operates to store charge up to a saturation value determined by its capacitance and an overflow capacitor is provided in an overflow region for storing charge above the saturation value of the floating diffusion capacitor. Readout at a high sensitivity level is provided when the floating diffusion capacitor is not saturated and readout at a lower sensitivity level is provided when there is saturation and subsequent overflow to the overflow region. Connection of the floating diffusion capacitor to the overflow capacitor shares the charge over the combined capacitance of the two capacitors and provides readout at a lower sensitivity without loss of charge.

First claim

What is claimed is:

1. A method for operating a light detection circuit comprising a first node, a second node, and a photodiode, the method comprising:
accumulating charge carriers via the photodiode;
while the photodiode is accumulating the charge carriers:
(i) connecting a reset voltage to the second node and connecting the second node to the first node;
(ii) isolating the second node from the reset voltage and isolating the first node from the second node, thereby generating a reference voltage at the first node; and
(iii) sampling the reference voltage;

transferring, from the photodiode, a first portion of the charge carriers to the first node and a second portion of the charge carriers to the second node;
sampling a first output voltage at the first node represented by the first portion of the charge carriers;
distributing the second portion of the charge carriers between the first node and the second node by connecting the first node to the second node; and
sampling a second output voltage represented by the first portion of the charge carriers and the second portion of the charge carriers distributed between the first node and the second node.

2. The method of claim 1 , further comprising determining a first corrected output voltage by comparing the reference voltage to the first output voltage.

3. The method of claim 1 ,
wherein the reference voltage is a first reference voltage,
wherein the second node is isolated from the reset voltage before the first node is isolated from the second node,
wherein isolating the second node from the reset voltage generates a second reference voltage at both the first node and the second node, the method further comprising:
sampling the second reference voltage prior to isolating the first node from the second node.

4. The method of claim 3 , further comprising determining a second corrected output voltage by comparing the second reference voltage to the second output voltage.

5. The method of claim 3 , further comprising storing the second reference voltage and the second output voltage.

6. The method of claim 1 , further comprising storing the reference voltage and the first output voltage.

7. The method of claim 1 , further comprising:
reconnecting the reset voltage to the second node, thereby connecting the first node to the reset voltage;
re-isolating the first node and the second node from the reset voltage, thereby generating a third reference voltage at both the first node and the second node; and
sampling the third reference voltage.

8. The method of claim 7 , further comprising determining a corrected output voltage by comparing the third reference voltage to the second output voltage.

9. A light detection circuit comprising a photodiode, a first node, a second node, a first switch, a second switch, and a third switch, the light detection circuit being configured to perform functions comprising:
accumulating charge carriers via the photodiode;
while the photodiode is accumulating the charge carriers:
(i) connecting, via the first switch, a reset voltage to the second node and connecting, via the second switch, the second node to the first node;
(ii) isolating, via the first switch, the second node from the reset voltage and isolating, via the second switch, the first node from the second node, thereby generating a reference voltage at the first node; and
(iii) sampling the reference voltage;

transferring, via the third switch from the photodiode, a first portion of the charge carriers to the first node and a second portion of the charge carriers to the second node;
sampling a first output voltage at the first node represented by the first portion of the charge carriers;
distributing, via the second switch, the second portion of the charge carriers between the first node and the second node by connecting the first node to the second node; and
sampling a second output voltage represented by the first portion of the charge carriers and the second portion of the charge carriers distributed between the first node and the second node.

10. A light detection circuit comprising: a first node, a second node, and
means for accumulating charge carriers;
means for, while the means for accumulating the charge carriers is accumulating the charge carriers:
(i) connecting a reset voltage to the second node and connecting the second node to the first node;
(ii) isolating the second node from the reset voltage and isolating the first node from the second node, thereby generating a reference voltage at the first node; and
(iii) sampling the reference voltage;

means for transferring, from the means for accumulating the charge carriers, a first portion of the charge carriers to the first node and a second portion of the charge carriers to the second node;
means for sampling a first output voltage at the first node represented by the first portion of the charge carriers;
means for distributing the second portion of the charge carriers between the first node and the second node by connecting the first node to the second node; and
means for sampling a second output voltage represented by the first portion of the charge carriers and the second portion of the charge carriers distributed between the first node and the second node.

Assignees

• Imec Vzw

Inventors

• Borremans Jonathan
• De Munck Koen

Classifications

• H04N25/59 Primary

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/616

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/621 Primary

  for the control of blooming · CPC title

• H04N25/627

  Detection or reduction of inverted contrast or eclipsing effects · CPC title

• H04N25/771

  comprising storage means other than floating diffusion · CPC title