Nonvolatile semiconductor memory system error correction capability of which is improved

Patent metadata

Field	Value
Publication number	US-9312885-B2
Application number	US-201213671936-A
Country	US
Kind code	B2
Filing date	Nov 8, 2012
Priority date	Aug 15, 2012
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.

First claim

What is claimed is:

1. A memory system comprising:
a memory cell array which includes a first storage area configured to store therein 1-bit data in one memory cell, and a second storage area configured to store therein data of a plurality of bits in one memory cell, to which the data is written in units of pages, and from which the data is read in units of pages, the second storage area including a plurality of blocks each of which is constituted of a plurality of pares, each of the plurality of blocks including an area configured to store therein data of the first storage area, and a redundant area including a page;
a first error correction part configured to generate first parity data in a row direction on the basis of the data, when the data is written to the first storage area;
a second error correction part configured to correct an error of the data on the basis of the first parity data read from the memory cell array; and
a third error correction part configured to generate second parity data in a column direction on the basis of data of a plurality of pages,
wherein the third error correction part generates the second parity data, when the data of the plurality of pages stored in the first storage area is transferred to the second storage area,
the second parity data is stored in the redundant area of the second storage area,
the second error correction part corrects an error of the data of the plurality of pages read from the second storage area on the basis of the first parity data, and
the third error correction part corrects an error of the data of the plurality of pages read from the second storage area on the basis of the second parity data, when the error cannot be corrected by the second error correction part.

2. The system according to claim 1 , wherein
the third error correction part generates the second parity data for each of the blocks.

3. The system according to claim 1 , wherein
each of the plurality of blocks includes a plurality of sub-blocks, and the third error correction part generates the second parity data for each of the plurality of sub-blocks.

4. The system according to claim 1 , wherein
the third error correction part generates third parity data in the column direction on the basis of the data of the plurality of pages, compares the third parity data, and the second parity data with each other to detect an error column, and corrects data of the detected error column.

5. The system according to claim 4 , wherein
the third error correction part comprises:
a plurality of EXOR circuits each of which includes first and second input ends, and an output end, and in each of which the data of each column of the data is supplied to the first input end; and
a plurality of registers each of which includes an input end, and an output end, and in each of which the input end is connected to the output end of corresponding one of the plurality of EXOR circuits, and the output end is connected to the second input end of the corresponding one of the plurality of EXOR circuits.

6. The system according to claim 5 , wherein
the third error correction part further comprises:
a plurality of comparators each of which includes first and second input ends, and an output end, and in each of which the output end of corresponding one of the plurality of registers is connected to the first input end, and the second parity data is supplied to the second input end; and
a plurality of correction circuits each of which includes first and second input ends, and an output end, and in each of which the first input end is connected to the output end of corresponding one of the plurality of comparators, and data including an error is supplied to the second input end,
wherein when an error cannot be corrected by the second error correction part, each of the plurality of comparators compares the third parity data supplied from each of the plurality of registers, and the second parity data with each other to detect an error column, and each of the plurality of correction circuits corrects the data of the detected error column.

7. An error correction method of a memory system comprising a memory cell array which includes a first storage area configured to store therein 1-bit data in one memory cell, and a second storage area configured to store therein data of a plurality of bits in one memory cell, to which the data is written in units of pages, and from which the data is read in units of pages, the second storage area including a plurality of blocks each of which is constituted of a plurality of pages, each of the plurality of blocks including an area configured to store therein data of the first storage area, and a redundant area including a page,
the method comprising:
generating, when data is written to the first storage area first parity data in a row direction on the basis of the data;
generating, when data stored in the first storage area is transferred to the second storage area, second parity data in a column direction on the basis of data of a plurality of pages read from the first storage area;
storing the second parity data in the redundant area of the second storage area;
correcting an error of data read from the second storage area in units of pages on the basis of the first parity data; and
correcting an error of the data of the plurality of pages read from the second storage area on the basis of the second parity data, when the error cannot be corrected by the first parity data.

8. The method according to claim 7 , further comprising:
generating third parity data in the column direction on the basis of the data of the plurality of pages of the second storage area;
comparing the second parity data, and the third parity data with each other to detect an error column; and
correcting the data of the detected error column.

9. The method according to claim 7 , wherein
the second parity data is generated for each of the blocks.

10. The method according to claim 7 , wherein
each of the plurality of blocks includes a plurality of sub-blocks, and the second parity data is generated for each of the plurality of sub-blocks.

Assignees

• Sakaue Kenji
• Kondo Yoshihisa
• Iwashiro Tarou
• Toshiba Kk

Inventors

• Sakaue Kenji
• Kondo Yoshihisa
• Iwashiro Tarou

Classifications

• G06F11/1044

  with specific ECC/EDC distribution · CPC title

• H03M13/2948

  Iterative decoding (H03M13/2957 takes precedence) · CPC title

• H03M13/2909 Primary

  Product codes · CPC title

• H03M13/293

  with erasure setting · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title