Systems and methods for capacitive digital to analog converters

Patent metadata

Field	Value
Publication number	US-9312877-B2
Application number	US-201514737928-A
Country	US
Kind code	B2
Filing date	Jun 12, 2015
Priority date	Sep 10, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A capacitive digital to analog converter (DAC) includes a first switching device that receives first, second, third, and fourth reference potentials at respective inputs and that selectively connects one of the first, second, third, and fourth reference potentials to a first output. The first and second reference potentials are approximately equal. The third and fourth reference potentials are approximately equal. A first capacitor is connected between the first output and a common node. A second switching device receives the first, second, third, and fourth reference potentials at respective inputs and selectively connects one of the first, second, third, and fourth reference potentials to a second output. A second capacitor is connected between the second output and the common node.

First claim

What is claimed is:

1. A capacitive digital to analog converter (DAC), comprising:
a first switching device that receives first, second, third, and fourth reference potentials at respective inputs and that selectively connects one of the first, second, third, and fourth reference potentials to a first output of the first switching device,
wherein the first and second reference potentials are approximately equal, and
wherein the third and fourth reference potentials are approximately equal;
a first capacitor that is connected between the first output of the first switching device and a common node;
a second switching device that receives the first, second, third, and fourth reference potentials at respective inputs and that selectively connects one of the first, second, third, and fourth reference potentials to a second output of the second switching device; and
a second capacitor that is connected between the second output of the second switching device and the common node.

2. The capacitive DAC of claim 1 wherein a first polarity of the first and second reference potentials is opposite that of a second polarity of the third and fourth reference potentials.

3. The capacitive DAC of claim 2 wherein a first magnitude of the first and second reference potentials is approximately equal to a second magnitude of the third and fourth reference potentials.

4. The capacitive DAC of claim 1 further comprising:
N additional switching devices that receive the first, second, third, and fourth reference potentials at respective input terminals and that selectively connect one of the first, second, third, and fourth reference potentials to respective outputs of the switching devices; and
N additional capacitors that are connected between the outputs of the N additional switching devices, respectively, and the common node,
wherein N is an integer greater than zero.

5. A successive-approximation-register (SAR) analog to digital converter (ADC) comprising:
the capacitive DAC of claim 1 ;
a comparator module that compares a first voltage of a sample of an analog signal with a second voltage at the common node; and
a SAR module that controls the first and second switching devices based on the comparison.

6. The SAR ADC of claim 5 wherein the SAR module:
controls the first and second switching devices to connect the first reference potential to the first and second outputs, respectively, at a first time; and,
when the second voltage is less than the first voltage at a second time that is after the first time, selectively controls the first and second switching devices to connect the second reference potential to the first and second outputs, respectively.

7. The SAR ADC of claim 6 wherein, when the second voltage is greater than the first voltage at the second time, the SAR module controls the first and second switching devices to connect the third reference potential to the first and second outputs, respectively.

8. The SAR ADC of claim 7 wherein, after controlling the first and second switching devices to connect the third reference potential to the first and second outputs, respectively, the SAR module selectively controls the first and second switching devices to connect the fourth reference potential to the first and second outputs, respectively.

9. The capacitive DAC of claim 1 wherein the first and second capacitors provide a radix of less than 2.

10. A capacitive digital to analog converter (DAC), comprising:
a first capacitor that includes a first terminal and a second terminal, the second terminal connected to a common node;
a first switching device that:
includes a third terminal connected to the first terminal of the first capacitor;
includes fourth and fifth terminals that are connected to first and second reference potentials, respectively, wherein the first and second reference potentials are approximately equal;
includes sixth and seventh terminals that are connected to third and fourth reference potentials, respectively, wherein the third and fourth reference potentials are approximately equal; and
selectively connects the third terminal to one of the fourth, fifth, sixth, and seventh terminals;

a second capacitor that includes an eighth terminal and a ninth terminal, the ninth terminal connected to the common node;
a second switching device that:
includes a tenth terminal connected to the eighth terminal of the second capacitor;
includes eleventh, twelfth, thirteenth, and fourteenth terminals that are connected to the first, second, third, and fourth reference potentials, respectively; and
selectively connects the tenth terminal to one of the eleventh, twelfth, thirteenth, and fourteenth terminals.

11. The capacitive DAC of claim 10 wherein a first polarity of the first and second reference potentials is opposite that of a second polarity of the third and fourth reference potentials.

12. The capacitive DAC of claim 11 wherein a first magnitude of the first and second reference potentials is approximately equal to a second magnitude of the third and fourth reference potentials.

13. A method of controlling switching of a capacitive digital to analog converter (DAC), the method comprising:
connecting, via a first switching device, a first reference potential to a first terminal of a first capacitor of the DAC,
wherein a second terminal of the first capacitor is connected to a common node of the DAC;
based on a first voltage of a sample of an analog signal and a second voltage at the common node of the DAC, connecting, via the first switching device, at least one of a second reference potential, a third reference potential, and a fourth reference potential to the first terminal of the first capacitor of the DAC,
wherein the first and second reference potentials are approximately equal, and
wherein the third and fourth reference potentials are approximately equal;
connecting, via a second switching device, the first reference potential to a third terminal of a second capacitor of the DAC,
wherein a fourth terminal of the second capacitor is connected to the common node of the DAC; and
based on the first voltage of the sample of the analog signal and the second voltage at the common node of the DAC, connecting, via the second switching device, at least one of the second reference potential, the third reference potential, and the fourth reference potential to the third terminal of the second capacitor of the DAC.

14. The method of claim 13 wherein a first polarity of the first and second reference potentials is opposite that of a second polarity of the third and fourth reference potentials.

15. The method of claim 14 wherein a first magnitude of the first and second reference potentials is approximately equal to a second magnitude of the third and fourth reference potentials.

16. The method of claim 13 further comprising, when the second voltage is less than the first voltage, via the first and second switching devices, connecting the second reference potential to the first and third terminals of the first and second capacitors, respectively.

17. The method of claim 16 further comprising, when the second voltage is greater than the first voltage, via the first and second switching devices, connecting the third reference potential to the first and third terminals of the first and second capacitors, respectively.

18. The method of claim 17 further comprising, after connecting the third reference potential to the first and third terminals of the first and second capacitors, respectively, connecting, via the first

Assignees

• Maxim Integrated Products

Inventors

• Strode Jonathan
• Himmelbauer Wolfgang

Classifications

• H03M1/0863 Primary

  of switching transients, e.g. glitches · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/466 Primary

  using switched capacitors · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title