Frequency and phase conversion circuit, wireless communication unit, integrated circuit and method therefor

Patent metadata

Field	Value
Publication number	US-9312816-B2
Application number	US-201414469564-A
Country	US
Kind code	B2
Filing date	Aug 26, 2014
Priority date	Sep 3, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A frequency and phase conversion circuit and wireless communication unit for supporting a plurality of different duty cycles is described. The frequency and phase conversion circuit comprises: a local oscillator module comprising a plurality of frequency conversion modules arranged to receive at least one input clock signal wherein a plurality of phases of the at least one input clock signal are selectable to support a plurality of different duty cycle clock signals; and at least one frequency conversion module comprising a plurality of mixer arrangements configured to receive at least one baseband input signal and the selected plurality of phases of the at least one input clock signal and output a frequency and phase converted representation of the at least one baseband input signal, wherein at least one of the plurality of mixer arrangements is re-used in a plurality of the selectable supportable duty cycles.

First claim

What is claimed is:

1. A frequency and phase conversion circuit for supporting a plurality of different duty cycle clock signals comprising:
a local oscillator module arranged to receive at least one input clock signal wherein a plurality of phases of the at least one input clock signal are selectable to support a plurality of different duty cycle clock signals;

and
a plurality of mixer arrangements configured to receive at least one baseband input signal and the selected plurality of phases of the at least one input clock signal and output a frequency and phase converted representation of the at least one baseband input signal;
wherein at least one of the plurality of mixer arrangements is re-used in a plurality of the selectable supportable duty cycles.

2. The frequency and phase conversion circuit of claim 1 wherein the number of mixer arrangements enabled is less than a total number of the plurality of phases of duty cycle clock signals supported by the frequency and phase conversion circuit.

3. The frequency and phase conversion circuit of claim 2 wherein the number (‘n’) of mixer arrangements enabled to output a required number of phase shifted waveforms is inversely proportional (1/n) to a duty cycle currently being supported from a plurality of selectable supportable duty cycles.

4. The frequency and phase conversion circuit of claim 2 wherein the number (‘n’) of mixer arrangements enabled corresponds to a number (‘n’) of local oscillator phases that are enabled.

5. The frequency and phase conversion circuit of claim 1 wherein a minimum number of mixer arrangements enabled to output a required number of phase shifted waveforms is inversely proportional to a minimum duty cycle being supported by the frequency and phase conversion circuit.

6. The frequency and phase conversion circuit of claim 1 wherein the local oscillator module comprises a plurality of dividers arranged to receive and divide a plurality of input clock signals to support the plurality of selectable supportable duty cycles.

7. The frequency and phase conversion circuit of claim 6 wherein the local oscillator module comprises at least one multiplexer configured to receive a plurality of output signals provided by each of the plurality of dividers and output a selected set of clock signals dependent upon a selected duty cycle.

8. The frequency and phase conversion circuit of claim 7 wherein the local oscillator module comprises an input configured to receive a switchable control to select a duty cycle to be enabled from the plurality of the selectable supportable duty cycles.

9. The frequency and phase conversion circuit of claim 1 wherein the local oscillator module further comprises asynchronous logic in cooperation with at least one divide-by-2N circuit, where N is a positive integer except zero, to generate an even number duty cycle clock signal.

10. The frequency and phase conversion circuit of claim 1 further comprising an arrangement of latches connected in series configured to receive an output from a multiplexer as a clock signal for the series of latches.

11. The frequency and phase conversion circuit of claim 10 wherein a minimum number (‘n’) of latches enabled is inversely proportional (1/n) to a selected duty cycle.

12. The frequency and phase conversion circuit of claim 11 wherein the number of enabled latches in series comprise at least four latches configured to support a 25% duty cycle clock signal and at least three latches to support a 33% duty cycle clock signal.

13. The frequency and phase conversion circuit of claim 10 wherein the arrangement of latches connected in series comprises one from a group of: a series of D-type flip flops, a series of shift registers.

14. The frequency and phase conversion circuit of claim 1 wherein the plurality of mixer arrangements comprise mixers configured to receive a plurality of baseband differential input signals, such that each of the plurality of mixer arrangements comprise at least two differential mixer stages.

15. The frequency and phase conversion circuit of claim 1 wherein the plurality of mixer arrangements comprise mixers configured to receive a plurality of baseband input signals, such that each of the plurality of mixer arrangements comprise at least two mixer stages configured for use in quadrature rejection.

16. The frequency and phase conversion circuit of claim 1 comprising a plurality of sliced frequency conversion modules with combined outputs.

17. An integrated circuit for supporting a plurality of different duty cycles, the integrated circuit comprising a frequency and phase conversion circuit slice comprising a plurality of mixer arrangements configured to receive at least one baseband input signal and a selected plurality of phases of at least one input clock signal and output a frequency and phase converted representation of the at least one baseband input signal wherein at least one of the plurality of mixer arrangements is re-used in a plurality of the selectable supportable duty cycles.

18. A wireless communication unit for supporting a plurality of different duty cycle clock signals, the wireless communication unit comprising a frequency and phase conversion circuit, wherein the frequency and phase conversion circuit comprises:
a local oscillator module arranged to receive at least one input clock signal wherein a plurality of phases of the at least one input clock signal are selectable to support a plurality of different duty cycle clock signals; and
a plurality of mixer arrangements configured to receive at least one baseband input signal and the selected plurality of phases of the at least one input clock signal and output a frequency and phase converted representation of the at least one baseband input signal wherein at least one of the plurality of mixer arrangements is re-used in a plurality of the selectable supportable duty cycles.

19. The wireless communication unit of claim 18 wherein a minimum number of mixer arrangements enabled to output a required number of phase shifted waveforms is inversely proportional to a minimum duty cycle being supported by the frequency and phase conversion circuit.

20. A method for frequency and phase conversion to support a plurality of different duty cycle clock signals, the method comprising:
receiving at least one input clock signal at a local oscillator generation circuit wherein a plurality of phases of the at least one input clock signal are selectable to support a plurality of different duty cycle clock signals;
enabling a number of mixer arrangements;
receiving at least one baseband input signal and a selected plurality of phases of the at least one input clock signal at a plurality of mixer arrangements; and
outputting a frequency and phase converted representation of the at least one baseband input signal;
wherein at least one of the plurality of mixer arrangements is re-used in a plurality of the selectable supportable duty cycles.

21. A frequency and phase conversion circuit for supporting a plurality of different duty cycles, comprising a plurality of mixer arrangements configured to receive at least one input signal and a selected plurality of phases of at least one input clock signal and output at least one baseband signal wherein at least one of the plurality of mixer arrangements is re-used in a plurality of the selectable supportable duty cycles.

22. A method for frequency and phase conversion to support a plurality of different duty cycle clock

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Fong Neric
• Lu Siu-Chuang Ivan

Classifications

• H03D7/1483 Primary

  comprising components for selecting a particular frequency component of the output · CPC title

• H03D7/1458

  Double balanced arrangements, i.e. where both input signals are differential · CPC title