DC-DC converter efficiency improvement and area reduction using a novel switching technique

Patent metadata

Field	Value
Publication number	US-9312758-B2
Application number	US-66151510-A
Country	US
Kind code	B2
Filing date	Mar 18, 2010
Priority date	Feb 25, 2010
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A control logic of a switched DC-to-DC converter allows continuous switching to bring the DC-to-DC converter to a final output value during a startup phase, it allows skipping of clock switching pulses if they are not needed and allows burst mode of switching pulses dependent on a load applied to the output voltage of the DC-to-DC converter. No digital or analog regulator is required for the control logic.

First claim

What is claimed is:

1. A method to improve the efficiency of a switched DC-to-DC converter, comprising the following steps:
(1) providing the switched-mode DC-to-DC converter comprising a charge pump and a control logic capable of controlling clock pulses of the DC-to-DC converter;
(2) applying continuous switching pulses initiated by the control logic to the DC-to-DC converter during a startup phase for a predetermined period of time to reach a desired output voltage;
(3) skipping cycles of the switching pulses if they are not needed during an operational phase wherein a skip control is determined by an expected load current demand on a charge pump output, wherein the expected load current is known by the control logic controlling a switching of a load on the charge pump, providing a forecast when the charge pump load will change, wherein the forecast is based on load switching transients; and
(4) applying a number of burst switching pulses, wherein a burst control is determined by the expected load current demand on the charge pump output;

wherein a stream of continuous pulses is generated for a fixed period of time; which, given a ratio of a capacitance of switched capacitor size to an output storage capacitance, determines the time taken to reach an un-loaded output voltage target.

2. The method of claim 1 wherein said switched-mode DC-to-DC converter is a buck converter.

3. The method of claim 1 wherein said switched-mode DC-to-DC converter is a boost converter.

4. The method of claim 1 wherein said switched-mode DC-to-DC converter is a buck-boost converter.

5. The method of claim 1 wherein said switched-mode DC-to-DC converter is of a switched capacitive type.

6. The method of claim 1 wherein a switching clock of the DC-to-DC converter is controlled by the control logic to start pulse skipping after the output voltage has reached the un-loaded output voltage target.

7. The method of claim 6 wherein a frequency of the pulse skipping can also be manually controlled.

8. The method of claim 1 wherein the control logic is also used to allow for a few continuous switching clocks to top-up the output voltage depending on the load applied to the output voltage.

9. The method of claim 8 wherein an efficiency of the DC-to-DC converter is improved because the skip mode and burst mode allows the DC-to-DC converter to skip cycles when they are not needed.

10. The method of claim 1 wherein a total number of charge pump clock pulses to an output voltage is minimized during load conditions based on the expected load current, wherein the control logic skips cycles of the charge pump clock pulses between burst clock cycles.

11. The method of claim 1 wherein in order to accommodate a charge pump to an increased load based on the expected load current a charge pump clock is set to burst mode which increases an available output current.

12. A system for a DC-to-DC converter having an improved efficiency, comprises:
a switched DC-to-DC converter comprising a charge pump; and
a control logic block, configured to control clock switching pulses of said switched DC-to-DC converter applying continuous switching pulses initiated by the control logic to the DC-to-DC converter during a startup phase for a predetermined period of time to reach a final output voltage and allowing the DC-to-DC converter to skip cycles when they are not needed, wherein a skip control is determined by an expected load current demand on a charge pump output and wherein the expected load current is known by the control logic controlling a switching of a load on the charge pump, providing a forecast when the charge pump load will change, wherein the forecast is based on load switching transients, and allowing a burst mode of clock switching pulses, wherein a burst control is determined by the expected load current demand on the charge pump and wherein the control block is configured to generate a stream of continuous pulses for a fixed period of time; which, given a ratio of a capacitance of switched capacitor size to an output storage capacitance, determines the time taken to reach an un-loaded output voltage target.

13. The system of claim 12 wherein said switched-mode DC-to-DC converter is a buck converter.

14. The system of claim 12 wherein said switched-mode DC-to-DC converter is a buck converter.

15. The circuit of claim 12 wherein said switched-mode DC-to-DC converter is a buck-boost converter.

16. The circuit of claim 12 wherein said switched-mode DC-to-DC converter is of a switched capacitive type.

Assignees

• Tyrrell Julian
• Minhas Biren
• Hedley Anna
• Levine Stuart
• Dialog Semiconductor Gmbh

Inventors

• Tyrrell Julian
• Minhas Biren
• Hedley Anna
• Levine Stuart

Classifications

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title