ESD protection circuit and ESD protection method thereof

Patent metadata

Field	Value
Publication number	US-9312691-B2
Application number	US-201414317166-A
Country	US
Kind code	B2
Filing date	Jun 27, 2014
Priority date	Oct 4, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

The present invention provides an ESD protection circuit including a discharge transistor, a first switch, a second switch, a third switch and a fourth switch. The discharge transistor forms a discharge path between a first voltage terminal and a second voltage terminal. The first switch selectively provides voltage at the first voltage terminal to a control terminal of the discharge transistor. The second switch selectively provides voltage at the second voltage terminal to the control terminal of the discharge transistor. The third switch selectively provides voltage at the first voltage terminal to a substrate of the discharge transistor. The fourth switch selectively provides voltage at second voltage terminal to the substrate of the discharge transistor.

First claim

What is claimed is:

1. An ESD protection circuit, comprising:
a first voltage terminal;
a second voltage terminal;
a discharge transistor, having a first terminal coupled to the first voltage terminal, a second terminal coupled to the second voltage terminal, a control terminal coupled to a first node, and a substrate coupled to a second node, wherein the discharge transistor forms a discharge path between the first voltage terminal and the second voltage terminal;
a first switch, coupled between the first voltage terminal and the first node, arranged to selectively provide voltage at the first voltage terminal to the control terminal of the discharge transistor;
a second switch, coupled between the first node and the second voltage terminal, arranged to selectively provide voltage at the second voltage terminal to the control terminal of the discharge transistor;
a third switch, coupled between the first voltage terminal and the second node, arranged to selectively provide voltage at the first voltage terminal to the substrate of the discharge transistor; and
a fourth switch, coupled between the second node and the second voltage terminal, arranged to selectively provide voltage at the second voltage terminal to the substrate of the discharge transistor.

2. The ESD protection circuit as claimed in claim 1 , wherein the discharge transistor is conductive when voltage at the first voltage terminal is greater than voltage at the second voltage terminal by a first predetermined value for discharging current of the first voltage terminal to the second voltage terminal, and the discharge transistor is conductive when voltage at the second voltage terminal is greater than voltage at the first voltage terminal by a second predetermined value for discharging current of the second voltage terminal to the first voltage terminal.

3. The ESD protection circuit as claimed in claim 2 , wherein the discharge transistor is an N-type field effect transistor, and when voltage at the first voltage terminal is greater than voltage at the second voltage terminal by the first predetermined value, the first switch is conductive for providing voltage at the first voltage terminal to the control terminal of the discharge transistor, and the fourth switch is conductive for providing voltage at the second voltage terminal to the substrate of the discharge transistor.

4. The ESD protection circuit as claimed in claim 3 , wherein when voltage at the second voltage terminal is greater than voltage at the first voltage terminal by the second predetermined value, the second switch is conductive for providing voltage at the second voltage terminal to the control terminal of the discharge transistor, and the third switch is conductive for providing voltage at the first voltage terminal to the substrate of the discharge transistor.

5. The ESD protection circuit as claimed in claim 4 , wherein the first switch is a first P-type field effect transistor having a first terminal coupled to the first voltage terminal, a second terminal coupled to the first node, a control terminal coupled to the second voltage terminal and a substrate coupled to the first voltage terminal.

6. The ESD protection circuit as claimed in claim 4 , wherein the first switch is a first N-type field effect transistor having a first terminal coupled to the first voltage terminal, a second terminal coupled to the first node, a control terminal coupled to the first voltage terminal and a substrate coupled to the second voltage terminal.

7. The ESD protection circuit as claimed in claim 4 , wherein the first switch is a first diode having an anode terminal coupled to the first voltage terminal and a cathode terminal coupled to the first node.

8. The ESD protection circuit as claimed in claim 4 , wherein the second switch is a second P-type field effect transistor having a first terminal coupled to the second voltage terminal, a second terminal coupled to the first node, a control terminal coupled to the first voltage terminal and a substrate coupled to the second voltage terminal.

9. The ESD protection circuit as claimed in claim 4 , wherein the second switch is a second N-type field effect transistor having a first terminal coupled to the second voltage terminal, a second terminal coupled to the first node, a control terminal coupled to the second voltage terminal and a substrate coupled to the first voltage terminal.

10. The ESD protection circuit as claimed in claim 4 , wherein the second switch is a second diode having an anode terminal coupled to the second voltage terminal and a cathode terminal coupled to the first node.

11. The ESD protection circuit as claimed in claim 4 , wherein the third switch is a third N-type field effect transistor having a first terminal coupled to the first voltage terminal, a second terminal coupled to the second node, a control terminal coupled to the second voltage terminal and a substrate coupled to the first voltage terminal.

12. The ESD protection circuit as claimed in claim 4 , wherein the fourth switch is a fourth N-type field effect transistor having a first terminal coupled to the second voltage terminal, a second terminal coupled to the second node, a control terminal coupled to the first voltage terminal and a substrate coupled to the second voltage terminal.

13. The ESD protection circuit as claimed in claim 2 , wherein the discharge transistor is P-type field effect transistor, and when voltage at the first voltage terminal is greater than voltage at the second voltage terminal by the first predetermined value, the second switch is conductive for providing voltage at the second voltage terminal to the control terminal of the discharge transistor, and the third switch is conductive for providing voltage at the first voltage terminal to the substrate of the discharge transistor.

14. The ESD protection circuit as claimed in claim 13 , wherein when voltage at the second voltage terminal is greater than voltage at the first voltage terminal by the second predetermined value, the first switch is conductive for providing voltage at the first voltage terminal to the control terminal of the discharge transistor, and the fourth switch is conductive for providing voltage at the second voltage terminal to the substrate of the discharge transistor.

15. The ESD protection circuit as claimed in claim 13 , wherein the first switch is a first N-type field effect transistor having a first terminal coupled to the first voltage terminal, a second terminal coupled to the first node, a control terminal coupled to the second voltage terminal and a substrate coupled to the first voltage terminal.

16. The ESD protection circuit as claimed in claim 13 , wherein the second switch is a second N-type field effect transistor having a first terminal coupled to the second voltage terminal, a second terminal coupled to the first node, a control terminal coupled to the first voltage terminal and a substrate coupled to the second voltage terminal.

17. The ESD protection circuit as claimed in claim 13 , wherein the third switch is a third P-type field effect transistor having a first terminal coupled to the first voltage terminal, a second terminal coupled to the second node, a control terminal coupled to the second voltage terminal and a substrate coupled to the first voltage terminal.

18. The ESD protection circuit as claimed in claim 13 , wherein the third switch is a third N-type field effect transistor having a first terminal coupled to the first voltage terminal, a second terminal coupled to the second node, a control te

Assignees

• Silicon Motion Inc

Inventors

• Chen Te-Wei

Classifications

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title