Solar cell and method for manufacturing the same

US9312420B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9312420-B2
Application numberUS-201313767748-A
CountryUS
Kind codeB2
Filing dateFeb 14, 2013
Priority dateApr 17, 2012
Publication dateApr 12, 2016
Grant dateApr 12, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A solar cell according to an embodiment of the invention includes a semiconductor substrate; an emitter layer formed at the semiconductor substrate, wherein the emitter layer includes a first portion of a first resistance and a second portion of a second resistance higher than the first resistance, wherein the first portion includes a first dopant and a second dopant having the same conductive type and the second portion including the second dopant; a passivation layer formed on the emitter layer, wherein the passivation layer includes the first dopant; and an electrode electrically connected to the first portion through the passivation layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a solar cell, the method comprising: preparing a semiconductor substrate; forming a passivation layer comprising a first dopant on a surface of the semiconductor substrate; forming a selective emitter layer by locally heating a portion of the passivation layer; forming an electrode electrically connected to a first portion of the selective emitter layer after the forming of the selective emitter layer; and forming a layer for a dopant layer by doping a second dopant having a conductive type the same as the first dopant to one surface of the semiconductor substrate between the preparing of the semiconductor substrate and the forming of the passivation layer, wherein, in the forming of the selective emitter layer, the first dopant of the heated portion of the passivation layer is diffused into an inside of the semiconductor substrate by the locally heating to form the selective emitter layer, wherein the forming of the selective emitter layer is a separate process from the forming of the electrode, wherein the first dopant has a conductive type different from that of the semiconductor substrate, wherein the selective emitter layer comprises a first portion in contact with the electrode and a second portion other than the first portion, wherein, in the forming of the selective emitter layer, the portion of the passivation layer corresponding to the first portion of the selective emitter layer where the electrode is connected is heated, and wherein, in the forming of the selective emitter layer, the portion of the passivation layer corresponding to the first portion of the selective emitter layer being heated and the first dopant being diffused into the semiconductor substrate results in the first portion having a resistance lower than that of the second portion. 2. The method according to claim 1 , wherein, in the forming of the selective emitter layer, a laser is irradiated to the portion of the passivation layer corresponding to the first portion. 3. The method according to claim 1 , wherein, in the forming of the selective emitter layer, the portion of the passivation layer corresponding to the first portion is heated to a temperature of about 1200 to 1600° C. 4. The method according to claim 2 , wherein an opening is formed by the laser at the portion of passivation layer corresponding to the first portion in the forming of the selective emitter layer. 5. The method according to claim 1 , wherein the first dopant and the second dopant are different from each other. 6. The method according to claim 1 , wherein the first dopant comprises aluminum, wherein the second dopant comprises boron, and wherein the passivation layer comprises aluminum oxide. 7. The method according to claim 1 , wherein the first dopant comprises bismuth, wherein the second dopant comprises phosphorus, and wherein the passivation layer comprises bismuth oxide. 8. The method according to claim 1 , wherein a concentration of the first dopant at the first portion is higher than a concentration of the second dopant at the first portion. 9. The method according to claim 1 , wherein, in the forming of the layer for the dopant layer, a thermal diffusion method or an ion-implantation method is used. 10. The method according to claim 1 , wherein the first dopant is a p-type, wherein the first dopant comprises aluminum, and wherein the passivation layer comprises aluminum oxide. 11. The method according to claim 1 , wherein the first dopant is an n-type, wherein the first dopant comprises bismuth, and wherein the passivation layer comprises bismuth oxide. 12. The method according to claim 1 , wherein the passivation layer has a thickness of about 5 to 20 nm. 13. The method according to claim 1 , further comprising: forming a back passivation layer including a third dopant and being formed at another surface of the semiconductor substrate; and forming a back surface field layer by locally heating a portion of the back passivation layer, wherein the third dopant of the back passivation layer is diffused into an inside of the semiconductor substrate by the locally heating.

Assignees

Inventors

Classifications

  • Monocrystalline silicon PV cells · CPC title

  • the coatings being antireflective or having enhancing optical properties · CPC title

  • Passivating · CPC title

  • The active layers comprising only Group IV materials · CPC title

  • Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

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What does patent US9312420B2 cover?
A solar cell according to an embodiment of the invention includes a semiconductor substrate; an emitter layer formed at the semiconductor substrate, wherein the emitter layer includes a first portion of a first resistance and a second portion of a second resistance higher than the first resistance, wherein the first portion includes a first dopant and a second dopant having the same conductive …
Who is the assignee on this patent?
Lg Electronics Inc
What technology area does this patent fall under?
Primary CPC classification H10F10/14. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 12 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).