Partially-blocked well implant to improve diode ideality with SiGe anode

Patent metadata

Field	Value
Publication number	US-9312358-B2
Application number	US-201213617140-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Sep 6, 2012
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a p-type substrate having an N-well formed from a portion of the p-type substrate via ion diffusion, wherein another portion of the p-type substrate blocked from ion diffusion forms an anode region and an interface between the N-well and the anode extends vertically from a top surface of the substrate to a bottom surface of the substrate;
a cavity formed to a selected depth in the anode region and adjacent the N-well;
a p-type doped region including p-type doped material deposited in the cavity of the anode adjacent the N-well, wherein the interface between the N-well and the anode provides a boundary of the p-type doped region and a p-n junction of the p-type doped region extends into the N-well and into the anode; and
a gate stack formed on the N-well, the gate stack including a spacer, wherein an outer sidewall of the spacer is substantially aligned with the vertical interface between the N-well and the anode.

2. The semiconductor device of claim 1 , wherein the N-well further is formed in the substrate via one of ion diffusion and ion implantation.

3. The semiconductor device of claim 2 , wherein the anode region is formed by covering the anode region prior to a doping process for forming the N-well.

4. The semiconductor device of claim 1 , wherein the N-well extends from an ion implantation surface of the substrate to a surface opposite the ion implantation surface of the substrate.

5. The semiconductor device of claim 1 , wherein the semiconductor device further includes a semiconductor diode.

6. The semiconductor device of claim 1 , wherein the substrate is a component of an integrated chip.

7. The semiconductor device of claim 1 , further comprising an electronic component formed at a surface of the substrate.

8. The semiconductor device of claim 1 , further comprising an n-type doped region in the N-well.

9. The semiconductor device of claim 8 , wherein the p-type doped region includes silicon germanium and the n-type doped region include silicon carbon.

10. A diode, comprising:
a p-type substrate having an N-well region formed from portion of the p-type substrate during ion doping, wherein a portion of the p-type substrate covered during ion doping forms an anode and an interface between the N-well and the anode extends vertically from a top surface of the substrate to a bottom surface of the substrate;
a cavity formed to a selected depth in the anode region and adjacent the N-well;
a p-type doped region including p-type doped material deposited in the cavity of the anode adjacent the N-well, wherein the interface between the N-well and the anode provides a boundary of the p-type doped region and a p-n junction of the p-type doped region extends into the N-well and into the anode; and
a gate stack formed on the N-well, the gate stack including a spacer, wherein an outer sidewall of the spacer is substantially aligned with the vertical interface between the N-well and the anode.

11. The diode of claim 10 , wherein ion doping further comprises one of ion diffusion and ion implantation.

12. The diode of claim 10 , wherein the N-well extends from an ion implantation surface of the substrate to a surface opposite the ion implantation surface of the substrate.

13. The diode of claim 10 , further comprising an electronic component formed at a surface of the substrate.

14. The diode of claim 10 , further comprising a diode formed on a substrate of an integrated chip.

15. A diode, comprising:
a p-type substrate having an N-well formed from a portion of the p-type substrate via ion doping and an anode formed from another portion of the p-type substrate by partial blocking the p-type substrate during ion doping, wherein an interface between the N-well and the anode extends vertically from a top surface of the substrate to a bottom surface of the substrate;
a cavity formed to a selected depth in the anode region and adjacent the N-well;
an extrinsically p-type doped region including p-type doped material deposited in the cavity of the anode adjacent the N-well, wherein the interface between the N-well and the anode provides a boundary of the p-type doped region and a p-n junction of the p-type doped region extends into the N-well and into the anode; and
a gate stack formed on the N-well, the gate stack including a spacer, wherein an outer sidewall of the spacer is substantially aligned with the vertical interface between the N-well and the anode.

16. The diode of claim 15 , further comprising the N-well resulting from one of ion implantation and ion diffusion.

17. The diode of claim 15 , further comprising an electronic component formed at a surface of the substrate.

Assignees

• Guo Dechao
• Haensch Wilfried E
• Wang Gan
• Wang Yanfeng
• Wang Xin
• IBM

Inventors

• Guo Dechao
• Haensch Wilfried E
• Wang Gan
• Wang Yanfeng
• Wang Xin

Classifications

• H10D12/211

  Gated diodes · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D12/021 Primary

  of gated diodes, e.g. field-controlled diodes [FCD] · CPC title

• H01L29/1608

  Electricity · mapped topic