Semiconductor packages and methods of packaging semiconductor devices

Patent metadata

Field	Value
Publication number	US-9312240-B2
Application number	US-201414521481-A
Country	US
Kind code	B2
Filing date	Oct 23, 2014
Priority date	Jan 30, 2011
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A method of forming semiconductor assemblies is disclosed. The method includes providing an interposer with through interposer vias. The interposer includes first and second surfaces. The through interposer vias extend from the first surface to the second surface of the interposer. The interposer with the through interposer vias enable attachment and electrical coupling of a die having very fine contact pitch to an external device having relatively larger contact pitch. At least a first die is mounted on at least one die attach region on the first surface of the interposer. The first die comprises a first surface with first conductive contacts thereon. The interposer comprises material with CTE similar to that of the first die. The first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer. A bonding process which does not require a reflow process is performed to form connections between the first die and interposer.

First claim

What is claimed is:

1. A method of forming semiconductor assemblies comprising:
providing an interposer with through interposer vias, the interposer comprises a first surface and a second surface, wherein
the through interposer vias extend from the first surface to the second surface of the interposer,
the first and second surfaces of the interposer comprise interposer contact pads thereon, the through interposer vias facilitate electrical coupling between the interposer contact pads on the first and second surfaces of the interposer, and
the second surface of the interposer comprises interposer contacts disposed thereon, the interposer contacts are configured to facilitate electrical coupling between the interposer contact pads and an external device;

mounting at least a first die on at least one die attach region on the first surface of the interposer, the first die comprises a first surface with first conductive contacts thereon, wherein the interposer comprises material with coefficient of thermal expansion (CTE) similar to that of the first die, the first conductive contacts of the first die are coupled to the through interposer vias on the first surface of the interposer; and
performing a bonding process which does not require a reflow process to form connections between the first die and interposer, wherein the bonding process comprises a thermal compression bonding process which comprises
aligning and contacting the first conductive contacts with the interposer contact pads,
elevating a temperature to be above a melting point of material of the first conductive contacts, and
applying a bond force to the first die to form an intermetallic bond between the first conductive contacts and the interposer contact pads.

2. The method in claim 1 comprising providing an underfill into a space between the first die and the first surface of the interposer.

3. The method of claim 2 wherein the underfill comprises a non-conductive paste.

4. The method of claim 3 wherein the non-conductive paste is provided through lamination, dispensing or spin coating technique.

5. The method of claim 2 wherein the underfill is provided prior to mounting at least a first die.

6. The method in claim 1 comprising mounting a second die on a second die attach region on the first surface of the interposer.

7. The method of claim 6 wherein the first and second dies are mounted in a side-by-side arrangement.

8. The method of claim 7 wherein performing the bonding process form connections between the first and second dies and interposer.

9. The method of claim 6 comprising providing underfills into spaces between the first and second dies and the first surface of the interposer.

10. The method of 9 wherein the underfills are provided prior to mounting the first and second dies.

11. The method of claim 6 comprising providing a package substrate having first and second surfaces, the first surface of the package substrate comprises first substrate contact pads, wherein the interposer is mounted on the first surface of the package substrate and the first substrate contact pads contact the interposer contacts on the second surface of the interposer.

12. The method of claim 11 comprising performing a bonding process which does not require a reflow process to form connections between the interposer and package substrate.

13. The method of claim 11 comprising performing a reflow process to form connections between the interposer and package substrate.

14. The method of claim 6 wherein the interposer contacts comprises conductive pillars having solder cap thereon.

15. The method of claim 6 comprising mounting a third device over the first die on a third die attach region on the first surface of the interposer, wherein the third die attach region is disposed on a periphery of the first die attach region and the third device comprises a first surface with conductive contacts thereon which directly contact the interposer contact pads which are disposed on the third die attach region.

16. The method of claim 1 comprising mounting a die stack on a second die attach region on the first surface of the interposer, wherein the die stack and the first die are mounted in a side-by-side arrangement.

17. A semiconductor assembly comprising:
an interposer with through interposer vias, the interposer comprises a first surface and a second surface, wherein
the through interposer vias extend from the first surface to the second surface of the interposer,
the first and second surfaces of the interposer comprise interposer contact pads thereon, the through interposer vias facilitate electrical coupling between the interposer contact pads on the first and second surfaces of the interposer, and
the second surface of the interposer comprises interposer contacts disposed thereon, the interposer contacts are configured to facilitate electrical coupling between the interposer contact pads and an external device;

at least first and second dies on first and second die attach regions on the first surface of the interposer, wherein the first and second dies are mounted in a side-by-side arrangement and the dies comprise a first surface with conductive contacts thereon, wherein the interposer comprises material with CTE similar to that of the dies, the conductive contacts of the dies are coupled to the through interposer vias on the first surface of the interposer; and
a third die disposed over the first die on a third die attach region on the first surface of the interposer, wherein the third die attach region is disposed on a periphery of the first die attach region and the third die comprises a first surface with conductive contacts thereon which directly contact the interposer contact pads which are disposed on the third die attach region.

Assignees

• United Test & Assembly Ct Lt
• Utac Headquarters Pte Ltd

Inventors

• Le Kriangsak Sae
• Chow Chee Kay

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title