Semiconductor device having an identification mark

Patent metadata

Field	Value
Publication number	US-9312226-B2
Application number	US-201213716004-A
Country	US
Kind code	B2
Filing date	Dec 14, 2012
Priority date	Dec 14, 2012
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A semiconductor device includes a chip, a contact pad arranged over the front side of the chip and an identification mark arranged over the contact pad. The identification mark includes an information about a property of the chip.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a contact pad arranged over a front side of a chip, and comprising a metallic material, wherein the contact pad comprises a side wall arranged at a periphery of the contact pad, wherein the side wall surrounds a flat surface of the contact pad and the side wall protrudes from the flat surface, wherein the side wall comprises a first surface facing the chip, an exposed second surface facing away from the chip, and an exposed side surface extending from the first surface to the second surface, wherein the side surface is arranged at the periphery of the contact pad and defines a boundary of the contact pad;
an active area arranged over the front side of the chip and adjacent to the contact pad, wherein the active area comprises an electronic component;
a conductive structure arranged under the contact pad, wherein the conductive structure forms at least a part of the electronic component;
a structured dielectric layer arranged under the contact pad, wherein the structured dielectric layer comprises a first section and a second section separated from the first section, wherein the structured dielectric layer forms at least a part of the electronic component, wherein a form of the side wall of the contact pad is similar to a form of the first section of the structured dielectric layer; and
an identification mark arranged over the contact pad and comprising a same metallic material as the contact pad, wherein the identification mark is separated from the side wall of the contact pad and protrudes from the flat surface of the contact pad, wherein the identification mark comprises information about a property of the chip, and wherein a form of the identification mark is similar to a form of the second section of the structured dielectric layer, wherein the contact pad physically contacts the conductive structure over a substantial area of the contact pad, and wherein the contact pad is separated from the conductive structure by the structured dielectric layer at the side wall of the contact pad and at the identification mark.

2. The semiconductor device of claim 1 , wherein the property of the chip comprises a date, a wafer number, and/or a type of the chip.

3. The semiconductor device of claim 1 , wherein the identification mark comprises a letter, a number, a bar code, a shape, and/or a symbol.

4. The semiconductor device of claim 1 , wherein the identification mark comprises a three-dimensional object.

5. The semiconductor device of claim 1 , wherein the identification mark is arranged in a non-peripheral region of the contact pad.

6. The semiconductor device of claim 1 , wherein the identification mark comprises a first region of the contact pad and a second region of the contact pad, wherein a level of the first region differs from a level of the second region.

7. The semiconductor device of claim 1 , wherein the identification mark has a dimension of at least 20 micrometers.

8. The semiconductor device of claim 1 , wherein the contact pad is essentially flat.

9. The semiconductor device of claim 1 , wherein the contact pad comprises a solder pad.

10. The semiconductor device of claim 1 , wherein the electronic component is selected from the group consisting of a diode, a transistor, and a fuse.

11. The semiconductor device of claim 1 , wherein an unused area of the active area is smaller than an area of the identification mark.

12. The semiconductor device of claim 1 , wherein the contact pad is electrically coupled to the conductive structure, the conductive structure comprising a conductive layer or a conductive via.

13. The semiconductor device of claim 1 , wherein the semiconductor device comprises a chip scale package.

14. A method, comprising:
providing a semiconductor wafer comprising at least one chip;
forming a contact pad over a front side of the chip and comprising a metallic material, wherein the contact pad comprises a side wall arranged at a periphery of the contact pad, wherein the side wall surrounds a flat surface of the contact pad and the side wall protrudes from the flat surface, wherein the side wall comprises a first surface facing the chip, an exposed second surface facing away from the chip, and an exposed side surface extending from the first surface to the second surface, wherein the side surface is arranged at the periphery of the contact pad and defines a boundary of the contact pad;
providing an active area arranged over the front side of the chip and adjacent to the contact pad, wherein the active area comprises an electronic component;
forming a conductive structure arranged under the contact pad, wherein the conductive structure forms at least a part of the electronic component; and
forming a structured dielectric layer arranged under the contact pad, wherein the structured dielectric layer comprises a first section and a second section separated from the first section, wherein the structured dielectric layer forms at least a part of the electronic component, wherein a form of the side wall of the contact pad is similar to a form of the first section of the structured dielectric layer, wherein an identification mark is arranged over the contact pad and comprising a same metallic material as the contact pad, wherein the identification mark is separated from the side wall of the contact pad and protrudes from the flat surface of the contact pad, wherein the identification mark comprises information about a property of the chip, wherein a form of the identification mark is similar to a form of the second section of the structured dielectric layer, wherein the contact pad physically contacts the conductive structure over a substantial area of the contact pad, and wherein the contact pad is separated from the conductive structure by the structured dielectric layer at the side wall of the contact pad and at the identification mark.

15. The method of claim 14 , wherein forming a structured dielectric layer comprises:
depositing a dielectric layer over the front side of the chip; and
structuring the dielectric layer.

16. The method of claim 15 , wherein forming the contact pad comprises depositing a conductive layer over the structured dielectric layer, wherein the conductive layer comprises the contact pad.

17. The semiconductor device of claim 1 , wherein the electronic component comprises a diode, wherein the conductive structure forms a finger structure of the diode, and wherein the structured dielectric layer forms an electric insulation between fingers of the finger structure.

Assignees

• Infineon Technologies Ag

Inventors

• Martens Stefan
• Schuderer Berthold
• Vaupel Mathias
• Peichl Raimund

Classifications

• H10W46/607

  Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title

• H10W46/401

  for identification or tracking · CPC title

• H10W46/106

  digital information, e.g. bar codes · CPC title

• H10W46/103

  alphanumeric information, e.g. words, letters or serial numbers · CPC title

• H10W46/101

  characterised by the type of information, e.g. logos or symbols · CPC title