Semiconductor device, electronic device including the same and manufacturing methods thereof

Patent metadata

Field	Value
Publication number	US-9312181-B2
Application number	US-201414531987-A
Country	US
Kind code	B2
Filing date	Nov 3, 2014
Priority date	Dec 11, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
etching a substrate using a first mask pattern formed on the substrate to form a trench;
forming a preliminary device isolation pattern filling the trench and including a first region and a second region, each of the first and second regions having a first thickness;
forming a second mask pattern on the first region;
etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form the second region having a second thickness smaller than the first thickness;
removing the first and second mask patterns; and
etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns.

2. The method of claim 1 , wherein the first mask pattern is removed by a phosphoric acid strip process, and
wherein the first mask pattern includes a nitride.

3. The method of claim 1 , wherein each of the preliminary fin-type active patterns has a rectangular shape extending in a first direction,
wherein the preliminary fin-type active patterns are spaced apart from each other in the first direction and a second direction perpendicular to the first direction,
wherein the first region of the preliminary device isolation pattern is formed between the preliminary fin-type active patterns spaced apart from each other in the first direction, and
wherein the second region of the preliminary device isolation pattern is formed between the preliminary fin-type active patterns spaced apart from each other in the second direction.

4. The method of claim 1 , wherein the second mask pattern is removed by an ashing process and/or a strip process, and
wherein the second mask pattern includes a photoresist pattern.

5. The method of claim 1 , wherein a top surface of the second region having the second thickness is disposed at a level higher than a top surface of the substrate.

6. The method of claim 5 , further comprising:
etching the second region having the second thickness to form a third thickness smaller than the second thickness,
wherein the top surface of the second region having the third thickness is disposed at a substantially same level as the top surface of the substrate.

7. The method of claim 1 , wherein etching the upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns comprises:
etching an upper portion of the first region of the preliminary device isolation pattern to form a first device isolation region of the device isolation pattern; and
etching an upper portion of the second region of the preliminary device isolation pattern to form a second device isolation region of the device isolation pattern,
wherein the first device isolation region of the device isolation pattern has a top surface disposed at a substantially same level as a top surface of the substrate, and
wherein the second device isolation region of the device isolation pattern has a top surface disposed at a level lower than the top surface of the substrate.

8. The method of claim 7 , further comprising:
forming pattern structures including a first pattern structure and a second pattern structure, the first pattern structure disposed on the first device isolation pattern, and the second pattern structure crossing over the preliminary fin-type active patterns and the second device isolation pattern;
etching the preliminary fin-type active patterns exposed by the pattern structures to form fin-type active patterns; and
forming dopant patterns on the fin-type active patterns at both sides of each of the pattern structures.

9. The method of claim 8 , wherein forming the pattern structures comprises:
sequentially forming an insulating layer and a material layer on the preliminary fin-type active patterns and the device isolation pattern;
planarizing a top surface of the material layer;
forming third mask patterns on the planarized material layer;
etching the planarized material layer and the insulating layer using the third mask patterns as an etch mask to form line patterns and insulating patterns; and
forming spacers on sidewalls of the line patterns and insulating patterns.

10. The method of claim 9 , wherein the line pattern of the first pattern structure has a third thickness on the first device isolation region,
wherein the line pattern of the second pattern structure has a fourth thickness on the fin-type active pattern and has a fifth thickness on the second device isolation region,
wherein the fourth thickness is substantially equal to the third thickness, and the fifth thickness is greater than the fourth thickness.

11. The method of claim 9 , further comprising:
forming an interlayer insulating layer on the substrate having the pattern structures and the dopant patterns;
removing the line patterns and insulating patterns of the pattern structures to form openings exposing the device isolation pattern and the fin-type active patterns; and
forming gate insulating patterns and gate electrodes in the openings to form gate structures.

12. A semiconductor device comprising:
a plurality of fin-type active patterns protruding from a substrate, each of the fin-type active patterns having a rectangular shape extending in a first direction, and the fin-type active patterns spaced apart from each other in the first direction and a second direction perpendicular to the first direction;
a device isolation pattern including a first device isolation region having a first thickness and a second device isolation region having a second thickness smaller than the first thickness, the first device isolation region disposed between the fin-type active patterns spaced apart from each other in the first direction, and the second device isolation region disposed between the fin-type active patterns spaced apart from each other in the second direction;
a first gate structure extending in the second direction on the first device isolation region, the first gate structure including a first insulating pattern and a first gate electrode;
a second gate structure extending in the second direction on the fin-type active patterns and the second device isolation region, the second gate structure including a second insulating pattern and a second gate electrode; and
dopant patterns disposed on the fin-type active patterns at both sides of the second gate structure,
wherein the thickness of the first gate electrode is substantially equal to the thickness of the second gate electrode disposed on the fin-type active pattern.

13. The semiconductor device of claim 12 , wherein a top surface of the first gate structure is disposed at a substantially same level as a top surface of the second gate structure.

14. The semiconductor device of claim 12 , wherein a top surface of the first device isolation region is disposed at a substantially same level as a top surface of the fin-type active pattern under the second gate structure.

15. The semiconductor device of claim 12 , wherein a top surface of the second device isolation region is lower than a top surface of the fin-type active pattern under the second gate structure.

16. A method of manufacturing an electronic device, comprising steps of:
forming a first mask pattern on a substrate;
etching the substrate using the first mask pattern to form a trench;
forming a preliminary device isolation pattern filling the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Yong-Joon
• Kim Myeongcheol
• Kim Cheol
• Seong Geumjung
• Lee Hak-Sun
• Jung Haegeon
• Han Ji-Eun

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D84/834

  comprising FinFETs · CPC title