Multilayer ceramic capacitor

US9312070B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9312070-B2
Application numberUS-201314033197-A
CountryUS
Kind codeB2
Filing dateSep 20, 2013
Priority dateSep 25, 2012
Publication dateApr 12, 2016
Grant dateApr 12, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multilayer ceramic capacitor has multiple laminated dielectric ceramic layers made of a dielectric ceramic, internal electrodes formed between the dielectric ceramic layers, and external electrodes electrically connected to the internal electrodes, wherein generation of cracks in the dielectric layer due to expansion of the internal electrode is suppressed by causing ceramic grains having a crystal axis ratio c/a higher than that of the ceramic grains constituting the dielectric layer to be present in non-contiguous parts of the internal electrodes between the dielectric ceramic layers, and by harnessing the stress-mitigating effect of domain switching involving these ceramic grains.

First claim

Opening claim text (preview).

We claim: 1. A multilayer ceramic capacitor having multiple laminated dielectric ceramic layers made of a dielectric ceramic, internal electrodes formed between the dielectric ceramic layers, and external electrodes electrically connected to the internal electrodes, each internal electrode including non-contiguous parts along a direction in which the internal electrode extends as a result of sintering, wherein: ceramic grains having a crystal axis ratio c/a are present in the non-contiguous parts of the internal electrodes between the dielectric ceramic layers by an area ratio of 15% or more in the non-contiguous parts as measured in a cross section in a thickness direction of the non-contiguous parts of the internal electrodes, wherein the crystal axis ratio c/a of the ceramic grains present in the non-contiguous parts of each internal electrode is higher than that of all ceramic grains constituting the dielectric ceramic layer in contact with the internal electrode. 2. A multilayer ceramic capacitor according to claim 1 , wherein an average grain size of the ceramic grains present in the non-contiguous parts is 0.15 to 3.00 μm. 3. A multilayer ceramic capacitor according to claim 1 , wherein a percentage of the internal electrode occupied by the ceramic is 8 to 40%. 4. A multilayer ceramic capacitor according to claim 2 , wherein a percentage of the internal electrode occupied by the ceramic is 8 to 40%. 5. A multilayer ceramic capacitor according to claim 1 , wherein the dielectric ceramic layer is made of a dielectric ceramic whose primary component is barium titanate perovskite solid solution. 6. A multilayer ceramic capacitor according to claim 2 , wherein the dielectric ceramic layer is made of a dielectric ceramic whose primary component is barium titanate perovskite solid solution. 7. A multilayer ceramic capacitor according to claim 3 , wherein the dielectric ceramic layer is made of a dielectric ceramic whose primary component is barium titanate perovskite solid solution. 8. A multilayer ceramic capacitor according to claim 4 , wherein the dielectric ceramic layer is made of a dielectric ceramic whose primary component is barium titanate perovskite solid solution.

Assignees

Inventors

Classifications

  • based on BaTiO3 perovskite phase · CPC title

  • Manganese oxides, manganates, rhenium oxides or oxide-forming salts thereof, e.g. MnO · CPC title

  • Nanotechnology for materials or surface science, e.g. nanocomposites · CPC title

  • Alkaline earth titanates · CPC title

  • Oxidative annealing · CPC title

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What does patent US9312070B2 cover?
A multilayer ceramic capacitor has multiple laminated dielectric ceramic layers made of a dielectric ceramic, internal electrodes formed between the dielectric ceramic layers, and external electrodes electrically connected to the internal electrodes, wherein generation of cracks in the dielectric layer due to expansion of the internal electrode is suppressed by causing ceramic grains having a c…
Who is the assignee on this patent?
Taiyo Yuden Kk
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 12 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).