Methods of operating memory devices

Patent metadata

Field	Value
Publication number	US-9312020-B2
Application number	US-201514686092-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	Jul 27, 2011
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data. The methods further include, in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells.

First claim

What is claimed is:

1. A method of operating a memory device, comprising:
applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data; and
in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells.

2. The method of claim 1 , further comprising applying the increasing sense voltage from an initial level to the particular level, wherein each of the data states is represented by a threshold voltage within a respective range of threshold voltages, and wherein each data state represented by a threshold voltage less than the particular level of the increasing sense voltage represents a particular logic level for the particular digit of data.

3. The method of claim 2 , wherein each data state represented by a threshold voltage greater than the particular level of the increasing sense voltage represents a second logic level for the particular digit of data, and wherein the second logic level is different than the particular logic level.

4. The method of claim 1 , in response to the increasing sense voltage reaching a second level greater than the particular level, initiating a transfer of data values of a second digit of data for each memory cell of the plurality of memory cells.

5. The method of claim 4 , further comprising continuing to apply the increasing sense voltage to the plurality of memory cells after initiating the transfer of data values of the second digit of data for each memory cell of the plurality of memory cells.

6. The method of claim 5 , in response to the increasing sense voltage reaching a third level greater than the second level, initiating a transfer of data values of a third digit of data for each memory cell of the plurality of memory cells.

7. The method of claim 6 , further comprising continuing to apply the increasing sense voltage to the plurality of memory cells after initiating the transfer of data values of the third digit of data for each memory cell of the plurality of memory cells.

8. The method of claim 4 , further comprising storing the data values of the particular digit of data for each memory cell of the plurality of memory cells and storing the data values of the second digit of data for each memory cell of the plurality of memory cells in register circuitry of the memory device.

9. The method of claim 8 , wherein initiating a transfer of the data values of the particular digit of data for each memory cell of the plurality of memory cells comprises initiating a transfer to shift the data values of the particular digit of data for each memory cell of the plurality of memory cells out of the register circuitry prior to storing all of the data values of the second digit of data for each memory cell of the plurality of memory cells in the register circuitry.

10. The method of claim 4 , further comprising:
completing the transfer of the data values of the particular digit of data for each memory cell of the plurality of memory cells before completing determining the second digit of data for each memory cell of the plurality of memory cells.

11. The method of claim 1 , wherein applying an increasing sense voltage to a plurality of memory cells comprises applying the increasing sense voltage to a control gate of each memory cell of the plurality of memory cells.

12. The method of claim 1 , wherein applying an increasing sense voltage to a plurality of memory cells comprises applying a stepped sense voltage to the plurality of memory cells.

13. A method of operating a memory device storing data states in memory cells, with each data state representing two or more digits of data, the method comprising:
applying an increasing sense voltage to control gates of a plurality of memory cells selected for a read operation, wherein each memory cell of the plurality of memory cells stores a respective data state representing two or more digits of data;
in response to the increasing sense voltage reaching a first level, initiating a transfer of data values of a first digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells; and
in response to the increasing sense voltage reaching a second level greater than the first level, initiating a transfer of data values of a second digit of data for each memory cell of the plurality of memory cells.

14. The method of claim 13 , further comprising applying the increasing sense voltage from an initial level to the first level, wherein each of the data states is represented by a threshold voltage within a respective range of threshold voltages, wherein each data state represented by a threshold voltage less than the first level of the increasing sense voltage represents a first logic level for the first digit of data, and wherein each data state represented by a threshold voltage greater than the first level of the increasing sense voltage represents a second, different, logic level for the first digit of data.

15. The method of claim 14 , further comprising applying the increasing sense voltage from the first level to the second level, wherein each data state represented by a threshold voltage greater than the first level of the increasing sense voltage and less than the second level of the increasing sense voltage represents a first logic level for the second digit of data, and wherein each data state represented by a threshold voltage greater than the second level of the increasing sense voltage represents a second, different, logic level for the second digit of data.

16. The method of claim 15 , wherein data states represented by a threshold voltage less than the first level of the increasing sense voltage represent either the first logic level or the second logic level for the second digit of data.

17. The method of claim 15 , wherein the first logic level for the first digit of data and the first logic level for the second digit of data are the same logic level, and wherein the second logic level for the first digit of data and the second logic level for the second digit of data are the same logic level.

18. The method of claim 13 , further comprising continuing to apply the increasing sense voltage to the plurality of memory cells after initiating the transfer of data values of the second digit of data for each memory cell of the plurality of memory cells.

19. A method of operating a memory device storing data states in memory cells, with each data state representing two or more digits of data, the method comprising:
applying an increasing sense voltage to control gates of a plurality of memory cells selected for a read operation, wherein each memory cell of the plurality of memory cells stores a respective data state representing two or more digits of data;
in response to the increasing sense voltage reaching a first level, initiating a transfer of data values of a first digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells;
in response to the increasing sense voltage reaching a second level greater than the first level, initiating a transfer of data values of a second digit of data for each memory cell of the plurality of memory cells while con

Assignees

• Micron Technology Inc

Inventors

• Hendrickson Nicholas

Classifications

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C7/1036

  using data shift registers · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/1033

  using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode · CPC title

• G11C16/34 Primary

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title