Non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9311994-B2
Application number	US-201414324110-A
Country	US
Kind code	B2
Filing date	Jul 4, 2014
Priority date	Jul 5, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

The invention concerns a memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data; wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration.

First claim

The invention claimed is:

1. A memory device comprising:
a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data and a first data latch coupled to said first resistive element; and
a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data and a second data latch coupled to said second resistive element and to said first data latch;
wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration; and
wherein a data storage node of said first data latch is coupled to an input node of the memory device for receiving an input data signal, and a data storage node of said second data latch is coupled to an output node of the memory device.

2. The memory device of claim 1 , wherein said second data retention duration is at least 50 percent shorter or longer than said first data retention duration.

3. The memory device of claim 1 , wherein said second data retention duration is at least 10 times shorter or longer than said first data retention duration.

4. The memory device of claim 1 , wherein a physical characteristic of the first resistive element is different from a corresponding physical characteristic of the second resistive element.

5. The memory device of claim 1 , wherein at least one dimension of said first resistive element is different from a corresponding dimension of said second resistive element.

6. A memory device comprising:
a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data and a first data latch coupled to said first resistive element; and
a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data and a second data latch coupled to said second resistive element and to said first data latch;
wherein:
said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration;
said first resistive element is programmable to have one of at least two resistive states and said first memory cell comprises a third resistive element, said first bit of data being represented by the relative resistances of the first and third resistive elements;
said second resistive element is programmable to have one of at least two resistive states and said second memory cell comprises a fourth resistive element, said second bit of data being represented by the relative resistances of the second and fourth resistive elements; and
the first resistive element is coupled between a first storage node of said first data latch and a first intermediate node, and the third resistive element is coupled between a second storage node of said first data latch and a second intermediate node, the first memory cell further comprising:
a first transistor of said first latch coupled between said first storage node and a first supply voltage;
a second transistor of said first latch coupled between said second storage node and said first supply voltage, wherein a control node of said first transistor is coupled to said second storage node and a control node of said second transistor is coupled to said first storage node;
a third transistor coupled between the first and second intermediate nodes; and
control circuitry configured to activate said third transistor while applying a second supply voltage to said first or second storage node to generate a programming current in a selected direction through said first and third resistive elements to program the resistive state of at least one of said elements.

7. The memory device of claim 6 , further comprising:
a fourth transistor coupled between said first intermediate node and said second supply voltage; and
a fifth transistor coupled between said second intermediate node and said second supply voltage, wherein said control circuitry is further configured to transfer the data value represented by the resistive states of said first and third resistive elements to said first and second storage nodes by activating said fourth and fifth transistors.

8. The memory device of claim 1 , wherein said first and second memory cells are each coupled to read-write circuitry comprising a latch and configured to transfer data between said first and second memory cells.

9. The memory device of claim 8 , wherein said first memory cell is coupled to said read-write circuitry via first and second bit lines, and wherein said second memory cell is coupled to said read-write circuitry via third and fourth bit lines.

10. The memory device of claim 1 , wherein each of said first and second resistive elements is one of:
a spin transfer torque element with in-plane anisotropy;
a spin transfer torque element with perpendicular-to-plane anisotropy;
a thermally assisted switching element;
a reduction oxide element;
a ferro-electric element; and
a phase change element.

11. A memory device comprising:
a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and
a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data;
wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration; and
wherein said first and second resistive elements are each spin transfer torque elements with in-plane anisotropy or perpendicular-to-plane anisotropy and formed of a plurality of stacked layers, wherein the volume of at least one of the layers of said first resistive element is different from a corresponding layer of said resistive second element.

12. A method of storing an input data value in non-volatile storage of a memory device, the memory device comprising a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data, wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration wherein said first and second resistive elements are each spin transfer torque elements with in-plane anisotropy or perpendicular-to-plane anisotropy and formed of a plurality of stacked layers, wherein the volume of at least one of the layers of said first resistive element is different from a corresponding layer of said resistive second element, the method comprising:
selecting, based on a data retention duration associated with said input data value, one of said first and second resistive elements; and
programming the selected resistive element to store the input data value.

Assignees

• Commissariat à l'énergie atomique et aux énergies alternatives
• Centre Nat Rech Scient

Inventors

• Di Pendina Grégory
• Javerliac Virgile

Classifications

• G11C13/0002 Primary

  using resistive RAM [RRAM] elements · CPC title

• G11C13/0021 Primary

  Auxiliary circuits · CPC title

• G11C11/165

  Auxiliary circuits · CPC title

• G11C14/0081

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C14/009

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title