Systems and methods of storing data

Patent metadata

Field	Value
Publication number	US-9311969-B2
Application number	US-201113329732-A
Country	US
Kind code	B2
Filing date	Dec 19, 2011
Priority date	Jul 22, 2011
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A method of writing data is performed in a data storage device with a controller and a memory. The memory includes latches and multiple storage elements and is operative to store a first number of bits in each storage element according to a first mapping of sequences of bits to states of the storage elements. The method includes loading data bits into the latches within the memory and generating manipulated data bits in the latches by manipulating designated data bits in the latches using one or more logical operations. The method also includes storing sets of the manipulated data bits to respective storage elements of the group of storage elements according to the first mapping. The designated data bits correspond to states of the respective storage elements according to a second mapping of sequences of bits to states. The second mapping is different than the first mapping.

First claim

What is claimed is:

1. A method of writing data, the method comprising: in a data storage device with a controller and a memory, wherein the memory includes latches and storage elements and wherein the memory is operative to store a first number of bits in each storage element according to a first mapping of bit sequences to states of the storage elements, performing: loading data bits into the latches within the memory; generating manipulated data bits in the latches by manipulating designated data bits of the data bits in the latches using one or more logical operations, wherein the first mapping is applied to undesignated data bits of the data bits, and wherein the manipulated data bits are generated by applying a second mapping, of the bit sequences to the states of the storage elements, to the designated data bits; storing the undesignated data bits to a first portion of a group of the storage elements; and storing the manipulated data bits to a second portion of the group of the storage elements, wherein the designated data bits correspond to states of the second portion of the group of the storage elements according to the second mapping, the second mapping different than the first mapping, wherein each logical page of a plurality of logical pages corresponding to the storage elements is associated with a respective error rate, wherein a first set of the data bits is stored in the plurality of logical pages based on the first mapping and a second set of the data bits is stored in the plurality of logical pages based on the second mapping, and wherein the manipulated data bits are generated by applying the second mapping to substantially equalize the error rates.

2. The method of claim 1 , wherein the latches and the storage elements are within a memory die that is configured to apply the first mapping as a built-in mapping and wherein the second mapping is created by loading the data bits into the latches and manipulating the data bits by logical register operations before storing the manipulated data bits.

3. The method of claim 2 , wherein the memory die includes circuitry to perform a state transformation of the designated data bits by applying the one or more logical register operations to the designated data bits.

4. The method of claim 1 , wherein the memory includes a flash multi-level cell (MLC) memory and wherein the group of the storage elements in a MLC word line.

5. The method of claim 4 , wherein the first mapping is associated with a first error rate corresponding to a first logical page of the MLC word line and wherein the second mapping is associated with a second error rate corresponding to the first logical page of the MLC word line, the second error rate lower than the first error rate.

6. The method of claim 1 , wherein a first group of the data bits is loaded into a first latch and wherein manipulating the designated data bits includes performing a logical NOT operation to each data bit of the first group of the data bits.

7. The method of claim 1 , wherein a first group of the data bits is loaded into a first latch and a second group of the data bits is loaded into a second latch, and wherein manipulating the designated data bits includes performing a bit-wise logical operation of the first group and the second group.

8. The method of claim 7 , wherein the bit-wise logical operation includes at least one of an AND operation and an OR operation.

9. The method of claim 7 , wherein the bit-wise logical operation includes a negated exclusive-OR (NOT-XOR) operation.

10. The method of claim 7 , wherein the bit-wise logical operation includes a swap operation.

11. The method of claim 1 , wherein the memory is configurable to selectively apply the second mapping.

12. The method of claim 1 , wherein a first portion of the latches contains the undesignated data bits, wherein a second portion of the latches contains the designated data bits, and wherein the manipulated data bits are generated at the second portion of the latches to apply the second mapping to the designated data bits to be stored at the second portion of the group of the storage elements while the first mapping is applied to the undesignated data bits to be stored at the first portion of the group of the storage elements.

13. The method of claim 12 , wherein the first portion of the group of the storage elements and the second portion of the group of the storage elements are in a single word line of a multi-level cell (MLC) flash memory, and wherein after applying the first mapping to the undesignated data bits and applying the second mapping to the designated data bits, error rates associated with each logical page of the plurality of logical pages that correspond to the single word line are substantially equalized.

14. The method of claim 12 , wherein the first portion of the group of the storage elements is at a first plane of a multi-plane flash memory and the second portion of the group of the storage elements is at a second plane of the multi-plane flash memory.

15. A data storage device, comprising: a memory including: storage elements; latches operative to latch data to be stored at a group of the storage elements; write circuitry operative to receive the data from the latches and to store a first number of bits in each storage elements of the group of the storage elements according to a first mapping of bit sequences to states of the storage elements; and mapping circuitry operative to generate manipulated data bits in the latches by manipulating designated data bits of the data using one or more logical operations, wherein the first mapping is applied to undesignated data bits of the data, and wherein the manipulated data bits are generated by applying a second mapping, of the bit sequences to the states of the storage elements, to the designated data bits, wherein the write circuitry is operative to store the undesignated data bits to a first portion of the group of the storage elements and to store the manipulated data bits to a second portion of the group of the storage elements, wherein the designated data bits correspond to states of the second portion of the group of the storage elements according to the second mapping, wherein the second mapping is different than the first mapping, wherein each logical page of a plurality of logical pages corresponding to the group of the storage elements is associated with a respective error rate, wherein a first set of data bits of the data is stored in the plurality of logical page based on the first mapping and a second set of data bits of the data is stored in the plurality of logical pages based on the second mapping, and wherein the manipulated data bits are generated by applying the second mapping to substantially equalize the error rates.

16. The data storage device of claim 15 , further comprising a controller coupled to the memory, wherein the mapping circuitry is configured to generate the manipulated data bits at the memory after the data has been received from the controller.

17. The data storage device of claim 15 , wherein the memory is configured to apply the first mapping as a built-in mapping and wherein the second mapping is created by loading the data into the latches and manipulating the designated data bits by logical register operations.

18. The data storage device of claim 15 , wherein the memory includes a flash multi-level cell (MLC) memory and wherein the group of the storage elements is a MLC word line.

19. The data storage device of claim 18 , wherein the first mapping is associated with a first error

Assignees

• Sharon Eran
• Alrod Idan
• Lasser Menahem
• Sandisk Technologies Inc

Inventors

• Sharon Eran
• Alrod Idan
• Lasser Menahem

Classifications

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/78

  using programmable devices · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title