Method and apparatus for monitoring general purpose input output, GPIO, signals

Patent metadata

Field	Value
Publication number	US-9311206-B2
Application number	US-201414253399-A
Country	US
Kind code	B2
Filing date	Apr 15, 2014
Priority date	Apr 15, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

An apparatus and method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC. The apparatus comprises a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of the SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins. A second checksum generation unit is adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins representing the GPIO bits. Checker logic is adapted to compare the first checksum generated by the first checksum generation unit with a second checksum generated by the second checksum generation unit.

First claim

The invention claimed is:

1. An apparatus for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC, said apparatus comprising:
a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of said system on chip, SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins of the GPIO port;
a second checksum generation unit adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins of the GPIO port representing the GPIO bits; and
a checker logic adapted to compare the first checksum generated by said first checksum generation unit with a second checksum generated by the second checksum generation unit to verify a match between both checksums.

2. The apparatus according to claim 1 ,
wherein the GPIO bits stored in the GPIO registers applied to said first checksum generation unit are masked by a first masking unit according to a bit masking pattern.

3. The apparatus according to claim 2 ,
wherein the analog signals at the GPIO pins of the GPIO port are converted to bits representing the analog signals at the GPIO pins.

4. The apparatus according to claim 3 ,
wherein the bits representing the analog signals at the GPIO pins are masked by a second masking unit according to a bit masking pattern.

5. The apparatus according to claim 4 ,
wherein the first masking unit and the second masking unit are programmable to select GPIO pins of the GPIO port to be monitored.

6. The apparatus according to claim 5 ,
wherein the first masking unit and the second masking unit are formed by a hardwired circuit to select GPIO pins of the GPIO port to be monitored.

7. The apparatus according to claim 1 ,
wherein if the first checksum generated by the first generation unit and the second checksum generated by the second generation unit do not match, the checker logic is adapted to indicate internally a failure of the checksum comparison to a control unit of the system on chip, SoC, and/or to output a comparison failure indication signal via at least one dedicated checker logic pin of the system on chip, SoC.

8. The apparatus according to claim 1 ,
wherein if the first checksum generated by the first checksum generation unit and the second checksum generated by the second checksum generation unit do not match, the checker logic is adapted to disable the GPIO port and/or to drive the GPIO pins to a safe I/O state by controlling the corresponding IO pad circuits.

9. The apparatus according to claim 1 ,
wherein if the first checksum generated by the first checksum generation unit and the second checksum generated by the second checksum generation unit do not match, the checker logic is adapted to switch off the GPIO registers.

10. The apparatus according to claim 1 ,
wherein the checker logic is an internal checker logic integrated in said system on chip, SoC, or is an external checker logic connected to the system on chip, SoC.

11. The apparatus according to claim 1 ,
wherein the second checksum generation unit and the second masking unit are integrated in said system on chip, SoC, or form external units connected to the GPIO pins of the GPIO port of said system on chip, SoC.

12. The apparatus according to claim 1 ,
wherein delay circuits are provided adapted to delay the first checksum and/or the second checksum received by the checker logic with a predetermined or adjustable delay time.

13. The apparatus according to claim 1 ,
wherein the checksum generation units are adapted to generate error correcting codes, ECC, as checksums compared by a comparator of said checker logic.

14. The apparatus according to claim 1 ,
wherein the first checksum generated by the first checksum generation unit and/or the second checksum generated by the second checksum generation unit are communicated via dedicated pins of said system on chip, SoC, and/or across a standard serial port of said system on chip, SoC, or other communication interface.

15. A microcontroller unit, MCU, comprising at least one apparatus according to claim 1 .

16. A method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC, said method comprising:
generating a first checksum depending on GPIO bits stored in GPIO registers of said system on chip;
generating a second checksum depending on analog GPIO signals at GPIO pins of the GPIO port representing the GPIO bits; and
comparing the first checksum and the second checksum to verify a match between both checksums.

17. The method according to claim 16 ,
wherein the analog signals at the GPIO pins of the GPIO port are converted to bits representing the analog signals at the GPIO pins and masking the bit representing the analog signals using a predetermined or programmable bit masking pattern.

18. The method according to claim 16 ,
wherein the GPIO bits stored in the GPIO registers are masked according to a predetermined or programmable bit masking pattern.

19. The method according to claim 16 ,
wherein if the first checksum and the second checksum do not match, a failure is indicated internally to a control unit and/or a comparison failure indication signal is output via at least one dedicated checker logic pin of the system on chip, SoC.

20. The method according to claim 16 ,
wherein if the first checksum and the second checksum do not match, the GPIO port is disabled and/or the GPIO pins of the GPIO port are driven to a safe I/O state.

21. The method according to claim 16 ,
wherein if the first checksum and the second checksum do not match, the GPIO registers are switched off.

22. The method according to claim 16 ,
wherein the first checksum and/or the second checksum are delayed with a predetermined or adjustable delay time.

23. The method according to claim 16 ,
wherein the first checksum and the second checksum are communicated via dedicated pins of the system on chip, SoC, and/or across a standard serial port of the system on chip, SoC.

24. The method according to claim 16 ,
wherein the first checksum and the second checksum are formed by error correcting codes, ECC.

Assignees

• Culshaw Carl
• Maiolani Mark
• Moran Robert F
• Freescale Semiconductor Inc

Inventors

• Culshaw Carl
• Maiolani Mark
• Moran Robert F

Classifications

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C2029/0409

  Online test · CPC title

• G06F11/3027 Primary

  where the computing system component is a bus · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G06F11/1608

  Error detection by comparing the output signals of redundant hardware (G06F11/1629, G06F11/1666 take precedence; error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18; checking static stores for correct operation G11C29/00; for logic circuits H03K19/003, H03K19/007; for pulse counters or frequency dividers H03K21/40) · CPC title