Intra-instructional transaction abort handling

Patent metadata

Field	Value
Publication number	US-9311101-B2
Application number	US-201213524370-A
Country	US
Kind code	B2
Filing date	Jun 15, 2012
Priority date	Jun 15, 2012
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

First claim

What is claimed is:

1. A system for intra-instructional transaction abort handling, the system comprising:
a processing circuit comprising transactional processing logic that determines whether an instruction is part of a transaction or non-transactional, an architected facility, and an architected facility buffer comprising one or more rename registers that store data temporarily until instruction completion moves the data to a targeted location, the processing circuit configured to perform a method comprising:
using an emulation routine to execute an instruction within a transaction, the instruction comprising at least one unit of operation, the transaction effectively delaying committing stores to memory until successful completion of the transaction;
setting a transaction block abort (TXBA) flag based on determining that the emulation of the instruction has made updates to one or more of: the architected facility and the architected facility buffer; and
based on receiving an abort indication, terminating the emulation of the instruction prior to completing the execution of the instruction, the terminating performed after completing, by the emulation routine, any previously initiated unit of operation of the instruction, wherein the terminating of the emulation of the instruction comprises:
rolling back any storage updates performed during the emulation of the instruction based on determining that the emulation of the instruction has made no updates to the architected facility and no updates to the architected facility buffer;
pausing the terminating of the emulation of the instruction after determining that the TXBA flag is set until all previously initiated units of operation of the instruction of the transaction have completed the emulation;
resetting the TXBA flag based on executing an end of emulation routine instruction or an emulation execution control reset transaction block abort instruction to start a new unit of operation; and
resuming the terminating of the emulation of the instruction based on determining the TXBA flag has been cleared.

2. The system of claim 1 , wherein the instruction is a single load instruction (SLI) and the instruction is flushed prior to the at least one unit of operation completing.

3. The system of claim 1 , wherein the instruction is a multi-load instruction (MLI), and the executing of the instruction further comprises performing one or more updates to the architected facility buffer.

4. The system of claim 3 , wherein the method further comprises resetting the one or more updates in the architected facility buffer based on receiving the abort indication.

5. The system of claim 1 , wherein the instruction is a long load instruction (LLI).

6. The system of claim 5 , wherein the LLI makes one or more updates to the architected facility and one or more updates to the architected facility buffer.

7. The system of claim 1 , wherein the method further comprises:
resetting the one or more updates to the architected facility buffer based on receiving the abort indication; and
retaining the one or more updates to the architected facility in response to the abort indication.

Assignees

• Belmar Brenton F
• Farrell Mark S
• Jacobi Christian
• Slegel Timothy J
• IBM

Inventors

• Belmar Brenton F
• Farrell Mark S
• Jacobi Christian
• Slegel Timothy J

Classifications

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/467

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F9/466

  Transaction processing · CPC title

• G06F9/30087 Primary

  Synchronisation or serialisation instructions · CPC title