Prefix computer instruction for compatibly extending instruction functionality

Patent metadata

Field	Value
Publication number	US-9311093-B2
Application number	US-201314100184-A
Country	US
Kind code	B2
Filing date	Dec 9, 2013
Priority date	Oct 3, 2011
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A prefix instruction is executed and passes operands to a next instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a target register of the prefix instruction execution.

First claim

What is claimed is:

1. A computer system for executing instructions, the system comprising:
a processor configured to communicate with a main storage, the processor comprising an instruction fetcher, an instruction optimizer and one or more execution units for executing optimized instructions, the processor configured to perform a method comprising:
obtaining a first instruction and a second instruction for execution, the first instruction preceding the second instruction in program order;
determining, by the processor, that the first instruction is a prefix instruction, the prefix instruction specifying a first value to be used as a result operand in executing the first instruction and a location for storing the result operand, the second instruction specifying a value to be used as a source operand in executing the second instruction and a location for fetching the source operand, wherein the result operand of the first instruction is the source operand of the second instruction;
executing the first instruction without storing the result operand at the location specified by the first instruction; and
executing the second instruction using the first value without fetching the source operand from the location specified by the second instruction.

2. The system according to claim 1 , the determining further comprising determining that there is no intervening interruption event between the execution of the first instruction and the second instruction.

3. The system according to claim 2 , wherein the first value to be used in executing the second instruction is identified as a result register of the first instruction, wherein the result register of the first instruction is a source register of the second instruction.

4. The system according to claim 3 , wherein the result register is an architected register associated with an architected instruction set, consisting of any one of a general register or a floating point register.

5. The system according to claim 2 , wherein the locations specified by the first and second instructions are main storage locations.

6. The system according to claim 1 , wherein the first value to be used comprises a result of executing the first instruction and an immediate field of the first instruction, the executing the second instruction further comprising using a concatenated value of at least part of the immediate field of the first instruction and an immediate field of the second instruction.

7. The system according to claim 1 , the method further comprising:
forming a single internal instruction based on the first instruction and second instruction, wherein the executing comprises executing the single internal instruction.

8. A computer program product for executing instructions, the computer program product comprising a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
obtaining a first instruction and a second instruction for execution, the first instruction preceding the second instruction in program order;
determining, by a processor, that the first instruction is a prefix instruction, the prefix instruction specifying a first value to be used as a result operand in executing the first instruction and a location for storing the result operand, the second instruction specifying a value to be used as a source operand in executing the second instruction and a location for fetching the source operand, wherein the result operand of the first instruction is the source operand of the second instruction;
executing the first instruction without storing the result operand at the location specified by the first instruction; and
executing the second instruction using the first value without fetching the source operand from the location specified by the second instruction.

9. The computer program product according to claim 8 , the determining further comprising determining that there is no intervening interruption event between the execution of the first instruction and the second instruction.

10. The computer program product according to claim 9 , wherein the first value to be used in executing the second instruction is identified as a result register of the first instruction, wherein the result register of the first instruction is a source register of the second instruction.

11. The computer program product according to claim 10 , wherein the result register is an architected register associated with an architected instruction set, consisting of any one of a general register or a floating point register.

12. The computer program product according to claim 9 , wherein the locations specified by the first and second instructions are main storage locations.

13. The computer program product according to claim 8 , wherein the first value to be used comprises a result of executing the first instruction and an immediate field of the first instruction, the executing the second instruction further comprising using a concatenated value of at least part of the immediate field of the first instruction and an immediate field of the second instruction.

14. The computer program product according to claim 8 , the method further comprising:
forming a single internal instruction based on the first instruction and second instruction, wherein the executing comprises executing the single internal instruction.

Assignees

• IBM

Inventors

• Gschwind Michael K
• Salapura Valentina

Classifications

• G06F9/384

  Register renaming · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30185 Primary

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title