Method and integrated device for analyzing liquid flow and liquid-solid interface interaction

Patent metadata

Field	Value
Publication number	US-9310285-B1
Application number	US-201414502897-A
Country	US
Kind code	B1
Filing date	Sep 30, 2014
Priority date	Sep 30, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

An Integrated Circuit (IC) chip with a lab-on-a-chip, a method of manufacturing the lab-on-a-chip and a method of using the lab-on-a-chip for fluid flow analysis in physical systems through combination with computer modeling. The lab-on-a-chip includes cavities in a channel layer and a capping layer, preferably transparent, covering the cavities. Gates control two dimensional (2D) lattice structures acting as heaters, light sources and/or sensors in the cavities, or fluid channels. The gates and two dimensional (2D) lattice structures may be at the cavity bottoms or on the capping layer. Wiring connects the gates and the 2D lattice structures externally.

First claim

What is claimed is:

1. An Integrated Circuit (IC) chip comprising:
a lab site;
one or more cavities in a channel layer at said lab site;
a capping layer covering said one or more cavities, said capping layer being transparent, wherein said capping layer includes at least one input/output port above at least one cavity, said input/output port for introducing fluid into, and removing fluid from, said cavity;
a two dimensional (2D) lattice structure at one surface of each of said one or more cavities;
a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure; and
wiring connecting the gates and the 2D lattice structures externally.

2. An IC chip as in claim 1 , wherein said 2D lattice structure is selected from a carbon nanotube film, graphene, transition metal dichalcogenides and black phosphorus.

3. An IC chip as in claim 2 , wherein said 2D lattice structure is a spin-on layer graphene.

4. An IC chip as in claim 1 , wherein at least one said 2D lattice structure is at the cavity surface opposite said capping layer.

5. An IC chip as in claim 1 , said at least one said 2D lattice structure is on one surface of said capping layer and the gate is on the opposite surface of said capping layer.

6. An IC chip as in claim 1 , further comprising:
one or more structural features in said at least one cavity, said one or more structural features modifying fluid flow through said at least one cavity;
a dielectric layer covering said 2D lattice structure; and
contacts through said dielectric layer to said 2D lattice structure, said wiring connecting to said 2D lattice structure through said contacts.

7. An IC chip as in claim 6 , wherein said one or more structural features comprise surface particles on internal cavity surfaces.

8. An IC chip as in claim 7 , wherein said cavity is 1-1000 microns long, 0.1-100 microns wide and deep, and said surface particles are nano-particles.

9. An IC chip as in claim 7 , wherein said cavity is 1-1000 microns long, 0.1-100 microns wide and deep, and said surface particles are 0.1-100 microns tall and wide.

10. An IC chip as in claim 9 , wherein said surface particles divide said cavity into a plurality of channels.

11. An IC chip as in claim 1 , wherein said gates and contact to said gates are transparent conductors, selected from Indium Tin Oxide (ITO) or a 2D lattice material.

12. An IC chip as in claim 1 , wherein at one or more cavity, said gate is one of a pair of gates separated from said cavity by the same said 2D lattice structure.

13. An Integrated Circuit (IC) chip comprising:
a lab site;
one or more cavities in a channel layer at said lab site;
a capping layer covering said one or more cavities, said capping layer being transparent;
a two dimensional (2D) lattice structure at one surface of each of said one or more cavities, wherein said 2D lattice structure is selected from a carbon nanotube film, graphene, transition metal dichalcogenides and black phosphorus;
a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure; and
wiring connecting the gates and the 2D lattice structures externally.

14. An IC chip as in claim 13 , wherein said 2D lattice structure is a spin-on layer graphene.

15. An Integrated Circuit (IC) chip comprising:
a lab site;
one or more cavities in a channel layer at said lab site;
a capping layer covering said one or more cavities, said capping layer being transparent;
one or more structural features in said at least one cavity, said one or more structural features modifying fluid flow through said at least one cavity;
a two dimensional (2D) lattice structure at one surface of each of said one or more cavities;
a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure;
a dielectric layer covering said 2D lattice structure;
contacts through said dielectric layer to said 2D lattice structure, said wiring connecting to said 2D lattice structure through said contacts; and
wiring connecting the gates and the 2D lattice structures externally.

16. An IC chip as in claim 15 , wherein said 2D lattice structure is selected from a carbon nanotube film, graphene, transition metal dichalcogenides and black phosphorus.

17. An IC chip as in claim 15 , wherein said one or more structural features comprise surface particles on internal cavity surfaces.

18. An IC chip as in claim 17 , wherein said cavity is 1-1000 microns long, 0.1-100 microns wide and deep, and said surface particles are nano-particles.

19. An IC chip as in claim 17 , wherein said cavity is 1-1000 microns long, 0.1-100 microns wide and deep, and said surface particles are 0.1-100 microns tall and wide.

20. An IC chip as in claim 19 , wherein said surface particles divide said cavity into a plurality of channels.

21. An Integrated Circuit (IC) chip comprising:
a lab site;
one or more cavities in a channel layer at said lab site;
a capping layer covering said one or more cavities, said capping layer being transparent;
a two dimensional (2D) lattice structure at one surface of each of said one or more cavities;
a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure; and
wiring connecting the gates and the 2D lattice structures externally, wherein said gates and contact to said gates are transparent conductors, selected from Indium Tin Oxide (ITO) or a 2D lattice material.

22. An Integrated Circuit (IC) chip comprising:
a lab site;
one or more cavities in a channel layer at said lab site;
a capping layer covering said one or more cavities, said capping layer being transparent;
a two dimensional (2D) lattice structure at one surface of each of said one or more cavities;
a gate at one said surface of at least one cavity, said gate being separated from said at least one cavity by said 2D lattice structure; and
wiring connecting the gates and the 2D lattice structures externally, wherein at one or more cavity, said gate is one of a pair of gates separated from said cavity by the same said 2D lattice structure.

Assignees

• IBM

Inventors

• Avouris Phaedon
• Engel Michael
• Feger Claudius
• Giro Ronaldo
• Ferreira Rodrigo
• Steiner Mathias

Classifications

• G01N33/24

  Earth materials (G01N33/42 takes precedence) · CPC title

• G01N21/71

  thermally excited · CPC title

• G01N11/04 Primary

  through a restricted passage, e.g. tube, aperture · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2111/10

  Numerical modelling · CPC title