Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Wiring substrate and semiconductor device
US9307641B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9307641-B2 |
| Application number | US-201514633525-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 27, 2015 |
| Priority date | Mar 3, 2014 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
A wiring substrate includes a first multi-layer wiring layer including an insulating layer formed of a non-photosensitive resin, a plurality of external connection pads formed on an upper face side of the first multi-layer wiring layer, and a second multi-layer wiring layer formed on the first multi-layer wiring layer, the second multi-layer wiring layer including an insulating layer formed of a photosensitive resin, the second multi-layer wiring layer having a wiring pitch narrower than the wiring pitch of the first multi-layer wiring layer. The external connection pads are exposed from the insulating layer of the second multi-layer wiring layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A wiring substrate, comprising: a first multi-layer wiring layer including an insulating layer formed of a non-photosensitive resin; a plurality of external connection pads formed on an upper face side of the first multi-layer wiring layer; and a second multi-layer wiring layer formed on the first multi-layer wiring layer, the second multi-layer wiring layer including an insulating layer formed of a photosensitive resin, the second multi-layer wiring lay…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9307641B2 cover?
- A wiring substrate includes a first multi-layer wiring layer including an insulating layer formed of a non-photosensitive resin, a plurality of external connection pads formed on an upper face side of the first multi-layer wiring layer, and a second multi-layer wiring layer formed on the first multi-layer wiring layer, the second multi-layer wiring layer including an insulating layer formed of …
- Who is the assignee on this patent?
- Shinko Electric Ind Co
- What technology area does this patent fall under?
- Primary CPC classification H10W70/685. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).