Audio processor circuits for acoustic echo cancellation and method therefor

Patent metadata

Field	Value
Publication number	US-9307318-B2
Application number	US-201313788471-A
Country	US
Kind code	B2
Filing date	Mar 7, 2013
Priority date	Mar 7, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

In one form, an audio processor circuit includes a first digital signal processing circuit, a second digital signal processing circuit, and an interleaver. The first digital signal processing circuit has an input for receiving a far-end audio signal, and an output. The second digital signal processing circuit has an input for receiving a digital near-end audio signal, and an output. The interleaver has a first input coupled to the output of the first digital signal processing circuit, a second input coupled to the output of the second digital signal processing circuit, and an output for alternatively providing signals received from the first and second inputs to the output.

First claim

What is claimed is:

1. An audio processor circuit comprising:
a first digital signal processing circuit having an input for receiving a far-end audio signal, and an output;
a second digital signal processing circuit having an input for receiving a digital near-end audio signal, and an output;
a delay buffer having an input coupled to said output of said first digital signal processing circuit, and an output, a delay of said delay buffer synchronizing said output of said first digital signal processing circuit to said output of said second digital signal processing circuit; and
an interleaver having a first input coupled to said output of said delay buffer, a second input coupled to said output of said second digital signal processing circuit, and an output for alternatively providing signals received from said first and second inputs to said output.

2. The audio processor circuit of claim 1 wherein said first digital signal processing circuit, said second digital signal processing circuit, and said interleaver are combined on a single integrated circuit chip.

3. The audio processor circuit of claim 2 wherein said single integrated circuit chip further comprises:
a digital-to-analog converter having an input coupled to said output of said first digital signal processing circuit, and an output for providing an analog audio signal; and
an analog-to-digital converter having an input for receiving a near-end audio signal, and an output for providing said digital near-end audio signal.

4. The audio processor circuit of claim 3 , wherein:
said delay of said delay buffer is approximately equal to a sum of a path delay through said digital-to-analog converter, a first attack echo path delay, a path delay through said analog-to-digital converter, and a path delay through said second digital signal processing circuit.

5. The audio processor circuit of claim 2 wherein said single integrated circuit chip further comprises:
a first serial interface circuit having an input coupled to at least one external input terminal, and an output coupled to said input of said first digital signal processing circuit; and
a second serial interface circuit having an input coupled to said output of said interleaver, and an output coupled to at least one external output terminal.

6. The audio processor circuit of claim 5 , wherein said first and second serial interface circuits are compliant with the Inter-IC Sound standard.

7. The audio processor circuit of claim 5 , further comprising:
a third serial interface circuit having an input coupled to said output of said second serial interface circuit, a first output for providing said output of said first digital signal processing circuit, and a second output for providing said output of said second digital signal processing circuit; and
an echo canceller having an input coupled to said output of said third serial interface circuit, and an output for providing an echo cancelled near-end audio signal.

8. The audio processor circuit of claim 7 , wherein said echo canceller comprises:
a summing device having a positive input coupled to said first output of said third serial interface circuit, a negative input, and an output for providing said echo cancelled near-end audio signal;
a tapped delay line having a signal input coupled to said first output of said third serial interface circuit, a coefficient input, and a signal output coupled to said negative input of said summing device; and
an adaptation control block having first and second inputs respectively coupled to said first and second outputs of said third serial interface circuit, a third input for receiving said far-end audio signal, a fourth input coupled to said output of said summing device, and an output coupled to said coefficient input of said tapped delay line.

9. The audio processor circuit of claim 7 , wherein said third serial interface circuit and said echo canceller are combined on a second integrated circuit chip.

10. The audio processor circuit of claim 1 , wherein said first digital processing circuit has a last stage comprising a first-in, first-out buffer, and wherein said delay buffer has an input coupled to an output of said first-in, first-out buffer.

11. The audio processor circuit of claim 1 , wherein said delay buffer comprises:
a first first-in, first-out (FIFO) buffer having an input coupled to said output of said first digital signal processing circuit, and an output, and providing a programmable delay;
a second FIFO buffer having a signal input coupled to said output of said first FIFO buffer, a control input, and an output, for providing a variable delay determined by said control input;
a cross correlation calculator having a first input coupled to said output of said first FIFO buffer, a second input coupled to said output of said second digital signal processing circuit, and an output for providing cross correlations for a plurality of delays; and
a determination block having an input coupled to said output of said cross correlation calculator and an output coupled to said control input of said second FIFO buffer, for providing said control input corresponding to a delay at a peak of said cross correlations.

12. The audio processor circuit of claim 1 , wherein:
said delay buffer further has an input coupled to said output of said second digital signal processing circuit, and an output for providing a fractional delay value; and
the audio processor circuit further comprises a digital-to-analog converter having an input coupled to said output of said delay buffer, and an output for providing an analog audio signal, wherein said digital-to-analog converter provides a fractional delay in said analog audio signal in response to said fractional delay value.

13. The audio processor circuit of claim 12 , wherein said delay buffer comprises:
a first first-in, first-out (FIFO) buffer having an input coupled to said output of said first digital signal processing circuit, and an output, and providing a fixed delay; and
a cross correlation calculator having a first input coupled to said output of said first FIFO buffer, a second input coupled to said output of said second digital signal processing circuit, and an output for providing said fractional delay value.

14. The audio processor circuit of claim 13 , wherein said digital-to-analog converter comprises:
an interpolator having an input forming said input of said digital-to-analog converter, and an output;
a delta-sigma modulator having an input coupled to said output of said interpolator, and an output;
a fractional delay buffer having a first input coupled to said output of said delta-sigma modulator, a second input coupled to said output of said cross correlation calculator, and an output; and
a filter having an input coupled to said output of said fractional delay buffer, and an output for providing said analog audio signal.

15. The audio processor circuit of claim 14 , wherein said fractional delay buffer comprises:
a plurality of delay elements coupled in a chain; and
a switch responsive to said fractional delay value for selecting an output from among said plurality of delay elements to provide as said output of said fractional delay buffer.

16. The audio processor circuit of claim 13 , wherein said digital-to-analog converter comprises:
an interpolator having a first input forming said input of said digital-to-analog converter, a second input for receiving said fractional delay value, and an output;
a delta-sigma modulator having an input coupled to said output of said interpolator, and an output
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Assignees

• Anderton David O
• Hung Kevin
• Taipale Dana
• Silicon Lab Inc

Inventors

• Anderton David O
• Hung Kevin
• Taipale Dana

Classifications

• H04B3/23

  using a replica of transmitted signal in the time domain, e.g. echo cancellers · CPC title

• H04M9/082

  using echo cancellers (echo cancellers per se H04B3/23) · CPC title

• H04R3/02 Primary

  for preventing acoustic reaction {, i.e. acoustic oscillatory feedback (specially adapted for hearing aids H04R25/453)} · CPC title